📄 mux8_1.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY mux8_1 IS;
port(c:in std_logic_vector(2 downto0);
dp: out std_logic;
a1,a2,a3,a4,b1,b2,t1,t2:in std_logic_vertor(3 downto ));
d:out std_logic_vector(3 downto 0));
end mux8_1;
architecture rt1 of mux8_1 is
begin
process(c,a1,a2,a3,a4,b1,b2,t1,t2)
variadle comb:std_logic_vector(2 downto 0);
begin
comb:=c;
case comb is
when"000"=>d<=a1;dp<='0';
when"001"=>d<=a2;dp<='0';
when"010"=>d<=a3;dp<='1';
when"011"=>d<=a4;dp<='0';
when"100"=>d<=b1;dp<='0';
when"101"=>d<=b2;dp<='0';
when"110"=>d<=t1;dp<='0';
when"111"=>d<=t2;dp<='0';
when others=>null;
end case;
end process;
end rt1;
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