📄 dsp28_initperipherals.pp
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extern struct CPUTIMER_VARS CpuTimer0;
extern struct CPUTIMER_VARS CpuTimer1;
extern struct CPUTIMER_VARS CpuTimer2;
struct PIECTRL_BITS {
Uint16 ENPIE:1;
Uint16 PIEVECT:15;
};
union PIECTRL_REG {
Uint16 all;
struct PIECTRL_BITS bit;
};
struct PIEIER_BITS {
Uint16 INTx1:1;
Uint16 INTx2:1;
Uint16 INTx3:1;
Uint16 INTx4:1;
Uint16 INTx5:1;
Uint16 INTx6:1;
Uint16 INTx7:1;
Uint16 INTx8:1;
Uint16 rsvd:8;
};
union PIEIER_REG {
Uint16 all;
struct PIEIER_BITS bit;
};
struct PIEIFR_BITS {
Uint16 INTx1:1;
Uint16 INTx2:1;
Uint16 INTx3:1;
Uint16 INTx4:1;
Uint16 INTx5:1;
Uint16 INTx6:1;
Uint16 INTx7:1;
Uint16 INTx8:1;
Uint16 rsvd:8;
};
union PIEIFR_REG {
Uint16 all;
struct PIEIFR_BITS bit;
};
struct PIEACK_BITS {
Uint16 ACK1:1;
Uint16 ACK2:1;
Uint16 ACK3:1;
Uint16 ACK4:1;
Uint16 ACK5:1;
Uint16 ACK6:1;
Uint16 ACK7:1;
Uint16 ACK8:1;
Uint16 ACK9:1;
Uint16 ACK10:1;
Uint16 ACK11:1;
Uint16 ACK12:1;
Uint16 rsvd:4;
};
union PIEACK_REG {
Uint16 all;
struct PIEACK_BITS bit;
};
struct PIE_CTRL_REGS {
union PIECTRL_REG PIECRTL;
union PIEACK_REG PIEACK;
union PIEIER_REG PIEIER1;
union PIEIFR_REG PIEIFR1;
union PIEIER_REG PIEIER2;
union PIEIFR_REG PIEIFR2;
union PIEIER_REG PIEIER3;
union PIEIFR_REG PIEIFR3;
union PIEIER_REG PIEIER4;
union PIEIFR_REG PIEIFR4;
union PIEIER_REG PIEIER5;
union PIEIFR_REG PIEIFR5;
union PIEIER_REG PIEIER6;
union PIEIFR_REG PIEIFR6;
union PIEIER_REG PIEIER7;
union PIEIFR_REG PIEIFR7;
union PIEIER_REG PIEIER8;
union PIEIFR_REG PIEIFR8;
union PIEIER_REG PIEIER9;
union PIEIFR_REG PIEIFR9;
union PIEIER_REG PIEIER10;
union PIEIFR_REG PIEIFR10;
union PIEIER_REG PIEIER11;
union PIEIFR_REG PIEIFR11;
union PIEIER_REG PIEIER12;
union PIEIFR_REG PIEIFR12;
};
extern volatile struct PIE_CTRL_REGS PieCtrl;
typedef interrupt void(*PINT)(void);
struct PIE_VECT_TABLE {
PINT PIE1_RESERVED;
PINT PIE2_RESERVED;
PINT PIE3_RESERVED;
PINT PIE4_RESERVED;
PINT PIE5_RESERVED;
PINT PIE6_RESERVED;
PINT PIE7_RESERVED;
PINT PIE8_RESERVED;
PINT PIE9_RESERVED;
PINT PIE10_RESERVED;
PINT PIE11_RESERVED;
PINT PIE12_RESERVED;
PINT PIE13_RESERVED;
PINT XINT13;
PINT TINT2;
PINT DATALOG;
PINT RTOSINT;
PINT EMUINT;
PINT XNMI;
PINT ILLEGAL;
PINT USER0;
PINT USER1;
PINT USER2;
PINT USER3;
PINT USER4;
PINT USER5;
PINT USER6;
PINT USER7;
PINT USER8;
PINT USER9;
PINT USER10;
PINT USER11;
PINT PDPINTA;
PINT PDPINTB;
PINT rsvd1_3;
PINT XINT1;
PINT XINT2;
PINT ADCINT;
PINT TINT0;
PINT WAKEINT;
PINT CMP1INT;
PINT CMP2INT;
PINT CMP3INT;
PINT T1PINT;
PINT T1CINT;
PINT T1UFINT;
PINT T1OFINT;
PINT rsvd2_8;
PINT T2PINT;
PINT T2CINT;
PINT T2UFINT;
PINT T2OFINT;
PINT CAPINT1;
PINT CAPINT2;
PINT CAPINT3;
PINT rsvd3_8;
PINT CMP4INT;
PINT CMP5INT;
PINT CMP6INT;
PINT T3PINT;
PINT T3CINT;
PINT T3UFINT;
PINT T3OFINT;
PINT rsvd4_8;
PINT T4PINT;
PINT T4CINT;
PINT T4UFINT;
PINT T4OFINT;
PINT CAPINT4;
PINT CAPINT5;
PINT CAPINT6;
PINT rsvd5_8;
PINT SPIRXINTA;
PINT SPITXINTA;
PINT rsvd6_3;
PINT rsvd6_4;
PINT MRINTA;
PINT MXINTA;
PINT rsvd6_7;
PINT rsvd6_8;
PINT rsvd7_1;
PINT rsvd7_2;
PINT rsvd7_3;
PINT rsvd7_4;
PINT rsvd7_5;
PINT rsvd7_6;
PINT rsvd7_7;
PINT rsvd7_8;
PINT rsvd8_1;
PINT rsvd8_2;
PINT rsvd8_3;
PINT rsvd8_4;
PINT rsvd8_5;
PINT rsvd8_6;
PINT rsvd8_7;
PINT rsvd8_8;
PINT RXAINT;
PINT TXAINT;
PINT RXBINT;
PINT TXBINT;
PINT ECAN0INTA;
PINT ECAN1INTA;
PINT rsvd9_7;
PINT rsvd9_8;
PINT rsvd10_1;
PINT rsvd10_2;
PINT rsvd10_3;
PINT rsvd10_4;
PINT rsvd10_5;
PINT rsvd10_6;
PINT rsvd10_7;
PINT rsvd10_8;
PINT rsvd11_1;
PINT rsvd11_2;
PINT rsvd11_3;
PINT rsvd11_4;
PINT rsvd11_5;
PINT rsvd11_6;
PINT rsvd11_7;
PINT rsvd11_8;
PINT rsvd12_1;
PINT rsvd12_2;
PINT rsvd12_3;
PINT rsvd12_4;
PINT rsvd12_5;
PINT rsvd12_6;
PINT rsvd12_7;
PINT rsvd12_8;
};
extern struct PIE_VECT_TABLE PieVectTable;
interrupt void INT13_ISR(void);
interrupt void INT14_ISR(void);
interrupt void DATALOG_ISR(void);
interrupt void RTOSINT_ISR(void);
interrupt void EMUINT_ISR(void);
interrupt void NMI_ISR(void);
interrupt void ILLEGAL_ISR(void);
interrupt void USER0_ISR(void);
interrupt void USER1_ISR(void);
interrupt void USER2_ISR(void);
interrupt void USER3_ISR(void);
interrupt void USER4_ISR(void);
interrupt void USER5_ISR(void);
interrupt void USER6_ISR(void);
interrupt void USER7_ISR(void);
interrupt void USER8_ISR(void);
interrupt void USER9_ISR(void);
interrupt void USER10_ISR(void);
interrupt void USER11_ISR(void);
interrupt void PDPINTA_ISR(void);
interrupt void PDPINTB_ISR(void);
interrupt void XINT1_ISR(void);
interrupt void XINT2_ISR(void);
interrupt void ADCINT_ISR(void);
interrupt void TINT0_ISR(void);
interrupt void WAKEINT_ISR(void);
interrupt void CMP1INT_ISR(void);
interrupt void CMP2INT_ISR(void);
interrupt void CMP3INT_ISR(void);
interrupt void T1PINT_ISR(void);
interrupt void T1CINT_ISR(void);
interrupt void T1UFINT_ISR(void);
interrupt void T1OFINT_ISR(void);
interrupt void T2PINT_ISR(void);
interrupt void T2CINT_ISR(void);
interrupt void T2UFINT_ISR(void);
interrupt void T2OFINT_ISR(void);
interrupt void CAPINT1_ISR(void);
interrupt void CAPINT2_ISR(void);
interrupt void CAPINT3_ISR(void);
interrupt void CMP4INT_ISR(void);
interrupt void CMP5INT_ISR(void);
interrupt void CMP6INT_ISR(void);
interrupt void T3PINT_ISR(void);
interrupt void T3CINT_ISR(void);
interrupt void T3UFINT_ISR(void);
interrupt void T3OFINT_ISR(void);
interrupt void T4PINT_ISR(void);
interrupt void T4CINT_ISR(void);
interrupt void T4UFINT_ISR(void);
interrupt void T4OFINT_ISR(void);
interrupt void CAPINT4_ISR(void);
interrupt void CAPINT5_ISR(void);
interrupt void CAPINT6_ISR(void);
interrupt void SPIRXINTA_ISR(void);
interrupt void SPITXINTA_ISR(void);
interrupt void MRINTA_ISR(void);
interrupt void MXINTA_ISR(void);
interrupt void SCIRXINTA_ISR(void);
interrupt void SCITXINTA_ISR(void);
interrupt void SCIRXINTB_ISR(void);
interrupt void SCITXINTB_ISR(void);
interrupt void ECAN0INTA_ISR(void);
interrupt void ECAN1INTA_ISR(void);
interrupt void PIE_RESERVED(void);
interrupt void rsvd_ISR(void);
struct SPIFFTX_BITS {
Uint16 TXFFIL:5;
Uint16 TXFFIENA:1;
Uint16 TXFFINTINTCLR:1;
Uint16 TXFFINT:1;
Uint16 TXFFST:5;
Uint16 TXFIFORESET:1;
Uint16 rsvd:1;
};
union SPIFFTX_REG {
Uint16 all;
struct SPIFFTX_BITS bit;
};
struct SPIFFRX_BITS {
Uint16 RXFFIL:5;
Uint16 RXFFIENA:1;
Uint16 RXFFINTCLR:1;
Uint16 RXFFINT:1;
Uint16 RXFFST:5;
Uint16 RXFIFORESET:1;
Uint16 RXFFOVFCLR:1;
Uint16 RXFFOVF:1;
};
union SPIFFRX_REG {
Uint16 all;
struct SPIFFRX_BITS bit;
};
struct SPIFFCT_BITS {
Uint16 TXDLY:8;
Uint16 rsvd:8;
};
union SPIFFCT_REG {
Uint16 all;
struct SPIFFCT_BITS bit;
};
struct SPICCR_BITS {
Uint16 SPICHAR:4;
Uint16 SPILBK:1;
Uint16 rsvd1:1;
Uint16 CLKPOLARITY:1;
Uint16 RESET:1;
Uint16 rsvd2:8;
};
union SPICCR_REG {
Uint16 all;
struct SPICCR_BITS bit;
};
struct SPICTL_BITS {
Uint16 SPIINTENA:1;
Uint16 TALK:1;
Uint16 MASTER_SLAVE:1;
Uint16 CLK_PHASE:1;
Uint16 OVERRUN:1;
Uint16 rsvd:11;
};
union SPICTL_REG {
Uint16 all;
struct SPICTL_BITS bit;
};
struct SPISTS_BITS {
Uint16 rsvd1:5;
Uint16 BUFFULL_FLAG:1;
Uint16 INT_FLAG:1;
Uint16 OVERRUN_FLAG:1;
Uint16 rsvd2:8;
};
union SPISTS_REG {
Uint16 all;
struct SPISTS_BITS bit;
};
struct SPIPRI_BITS {
Uint16 rsvd1:4;
Uint16 FREE:1;
Uint16 SOFT:1;
Uint16 PRIORITY:1;
Uint16 rsvd2:9;
};
union SPIPRI_REG {
Uint16 all;
struct SPIPRI_BITS bit;
};
struct SPI_REGS {
union SPICCR_REG SPICCR;
union SPICTL_REG SPICTL;
union SPISTS_REG SPISTS;
Uint16 rsvd1;
Uint16 SPIBRR;
Uint16 rsvd2;
Uint16 SPIRXEMU;
Uint16 SPIRXBUF;
Uint16 SPITXBUF;
Uint16 SPIDAT;
union SPIFFTX_REG SPIFFTX;
union SPIFFRX_REG SPIFFRX;
union SPIFFCT_REG SPIFFCT;
Uint16 rsvd3[2];
union SPIPRI_REG SPIPRI;
};
extern volatile struct SPI_REGS SpiaRegs;
extern volatile struct SPI_REGS SpibRegs;
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