inits.s

source code of armboot for s3c4510

    MOV     r0, #0
    STR     r0, [r1]

    LDR     r1, =ASIC_EIO_WDSCON
    MOV     r0, #0
    STR     r0, [r1]
#endif


    /*-----------------------------------*
     * Initialize STACK
     *-----------------------------------*/
    MRS     r0, CPSR
    BIC     r0, r0, #IFRQ_MASK | MODE_MASK
    ORR     r2, r0, #USR_MODE           // r2 == USR mode, interrupt enable, for setup SPSR

    // set UND mode and set up stack pointer
    ORR     r1, r0, #IFRQ_DISABLE | UND_MODE
    MSR     CPSR, r1
    MSR     SPSR, r2
    LDR     sp, =STACK_UND

    // set ABT mode and set up stack pointer
    ORR     r1, r0, #IFRQ_DISABLE | ABT_MODE
    MSR     CPSR, r1
    MSR     SPSR, r2
    LDR     sp, =STACK_ABT

    // set IRQ mode and set up stack pointer
    ORR     r1, r0, #IFRQ_DISABLE | IRQ_MODE
    MSR     CPSR, r1
    MSR     SPSR, r2
    LDR     sp, =STACK_IRQ

    // set FIQ mode and set up stack pointer
    ORR     r1, r0, #IFRQ_DISABLE | FIQ_MODE
    MSR     CPSR, r1
    MSR     SPSR, r2
    LDR     sp, =STACK_FIQ

    // set SVC mode and set up stack pointer
    ORR     r1, r0, #IFRQ_DISABLE | SVC_MODE
    MSR     CPSR, r1
    MSR     SPSR, r2
    LDR     sp, =STACK_SVC              // now, return to SVC mode


    /*-----------------------------------*
     * Exception Vector Table Setup
     *-----------------------------------*/
    // Otherwise we copy a sequence of LDR PC instructions over the vectors
    // (Note: We copy LDR PC instructions because branch instructions
    // could not simply be copied, the offset in the branch instruction
    // would have to be modified so that it branched into ROM. Also, a
    // branch instructions might not reach if the ROM is at an address
    // > 32M).
    MOV     r8, #0
    ADRL    r9, ExcptHndlr_Vector_Init
    LDMIA   r9!, {r0-r7}
    STMIA   r8!, {r0-r7}
    LDMIA   r9!, {r0-r7}
    STMIA   r8!, {r0-r7}


    /*-----------------------------------*
     * Initialize memory for C code
     *-----------------------------------*/
    LDR     r0, =_text_end              // Get pointer to ROM data
    LDR     r1, =_data_base             // and RAM copy
    LDR     r3, =_bss_base              // Zero init base => top of initialised data
    CMP     r0, r1                      // Check that they are different
    BEQ     BSS_Clear
ROM_Vars_Loop:
    CMP     r1, r3                      // Copy init data (RW data) from ROM space to RAM space
    LDRCC   r2, [r0], #4
    STRCC   r2, [r1], #4
    BCC     ROM_Vars_Loop

BSS_Clear:
    LDR     r1, =_bss_end               // Top of zero init segment
    MOV     r2, #0
BSS_Loop:
    CMP     r3, r1                      // Zero init the region from |Image$$ZI$$Base|
    STRCC   r2, [r3], #4                // to |Image$$ZI$$Limit|
    BCC     BSS_Loop

    /*-----------------------------------*
     * Init MMU
     *-----------------------------------*/
    BL      MMU_vInit

    /*-----------------------------------*
     * Now change to user mode and set
     * up user mode stack
     * and enable IRQ/FIQ
     *-----------------------------------*/
    MRS     r0, CPSR
    BIC     r0, r0, #IFRQ_MASK | MODE_MASK
    ORR     r0, r0, #USR_MODE
    MSR     CPSR, r0
    LDR     sp, =STACK_USR

    /*-----------------------------------*
     * Now we enter the C Program
     *-----------------------------------*/
  //  BL      Main_Entry
  	/* set up the stack */
	ldr	r0, _armboot_end
	add	r0, r0, #CONFIG_STACKSIZE
	sub	sp, r0, #12		/* leave 3 words for abort-stack */
	
	ldr	pc, _start_armboot
		
	_start_armboot:	.word start_armboot




/*---------------------------------------*
 * Get CPSR
 *---------------------------------------*/
CPUS_u32GetCPSR:
    // Corrupts r0 (okay during -apcs use)
    MRS     r0, CPSR
    BIC     r0, r0, #FLAG_MASK          // clear flag bits
    BIC     r0, r0, #IFRQ_MASK          // enable IFRQ, this is for KNL_TSK_vSchedule()
                                        // to enable interrupt at context switch
    MOV     pc, lr


/*---------------------------------------*
 * Get SP
 *---------------------------------------*/
CPUS_u32GetSP:
    // Corrupts r0 (okay during -apcs use)
    MOV     r0, sp
    MOV     pc, lr


/*--------------------------------------*
 * Trap to SVC Mode
 *--------------------------------------*/
CPUS_vTrapKernelMode:
    MOV     r0, lr
    SWI     0xFF
    MOV     pc, r0


/*--------------------------------------*
 * Get System Mode
 *--------------------------------------*/
CPUS_u32GetMode:
    MRS     r0, CPSR                    // r0 = CPSR
    AND     r0, r0, #MODE_MASK          // r0 &= MODE_MASK
    MOV     pc, lr                      // return to caller


/*--------------------------------------*
 * Initialize Memory Protection Region
 *--------------------------------------*/
MMU_vInit:
    STMFD   sp!, {r0-r12,lr}                // Prolog
    /*----------------------------------*
     * Disable Prototection Unit, DCache, ICache
     * Flush ICACHE, DCACHE, Drain Write Buffer
     *----------------------------------*/
    BL      MMUS_vCacheDisable

    /*----------------------------------*
     * Set CP15[2], Instruction and Data Cache Register
     *----------------------------------*/
    MOV     r0, #1                          // Cache Region 0 only
    MCR     p15, 0, r0, c2, c0, 0           // Set Data-Cacheable
    MCR     p15, 0, r0, c2, c0, 1           // Set Inst-Cacheable

    /*----------------------------------*
     * Set CP15[5] Code/Data region permission
     *----------------------------------*/
    LDR     r0, =0xFFFF                     // Enable all regions
    MCR     p15, 0, r0, c5, c0, 0           // Data-Space permission
    MCR     p15, 0, r0, c5, c0, 1           // Code-Space permission

    /*----------------------------------*
     * Set CP15[6] Code/Data region setting
     *----------------------------------*/
    LDR     r0, =MMU_REGION0                // Set Region 0
    MCR     p15, 0, r0, c6, c0, 0           // Data Region0
    MCR     p15, 0, r0, c6, c0, 1           // Code Region0

    LDR     r0, =MMU_REGION1                // Set Region 1
    MCR     p15, 0, r0, c6, c1, 0           // Data Region1
    MCR     p15, 0, r0, c6, c1, 1           // Code Region1

    LDR     r0, =MMU_REGION2                // Set Region 2
    MCR     p15, 0, r0, c6, c2, 0           // Data Region2
    MCR     p15, 0, r0, c6, c2, 1           // Code Region2

    LDR     r0, =MMU_REGION3                // Set Region 3
    MCR     p15, 0, r0, c6, c3, 0           // Data Region3
    MCR     p15, 0, r0, c6, c3, 1           // Code Region3

    LDR     r0, =MMU_REGION4                // Set Region 4
    MCR     p15, 0, r0, c6, c4, 0           // Data Region4
    MCR     p15, 0, r0, c6, c4, 1           // Code Region4

    LDR     r0, =MMU_REGION5                // Set Region 5
    MCR     p15, 0, r0, c6, c5, 0           // Data Region5
    MCR     p15, 0, r0, c6, c5, 1           // Code Region5

    LDR     r0, =MMU_REGION6                // Set Region 6
    MCR     p15, 0, r0, c6, c6, 0           // Data Region6
    MCR     p15, 0, r0, c6, c6, 1           // Code Region6

    LDR     r0, =MMU_REGION7                // Set Region 7
    MCR     p15, 0, r0, c6, c7, 0           // Data Region7
    MCR     p15, 0, r0, c6, c7, 1           // Code Region7

    /*----------------------------------*
     * Enable I Cache, DCache, Protection Unit
     *----------------------------------*/
    BL      MMUS_vCacheEnable

    LDMFD   sp!, {r0-r12,pc}                // Epilog


/*--------------------------------------*
 * Enable Protection Bit in CP15[1] bit 0
 *--------------------------------------*/
MMUS_vCacheEnable:
    // Corrupts r0-r1 (okay during -apcs use)
    LDR     r1, =(MMU_PROTECT_ENABLE | MMU_DCACHE_ENABLE | MMU_ICACHE_ENABLE)
    MRC     p15, 0, r0, c1, c0, 0           // r0 = CP15[1]
    ORR     r0, r0, r1                      // r0 = r0 | r1
    MCR     p15, 0, r0, c1, c0, 0           // Write CP15[1]
    MOV     pc, lr                          // Return to caller


/*--------------------------------------*
 * Disable Protection Bit in CP15[1] bit 0
 *--------------------------------------*/
MMUS_vCacheDisable:
    // Corrupts r0-r1 (okay during -apcs use)
    LDR     r1, =~(MMU_PROTECT_ENABLE | MMU_DCACHE_ENABLE | MMU_ICACHE_ENABLE)
    MRC     p15, 0, r0, c1, c0, 0           // r0 = CP15[1]
    AND     r0, r0, r1                      // r0 = r0 & r1
    MCR     p15, 0, r0, c1, c0, 0           // Write CP15[1]
    /*--------------------------------------*
     * Flush ICache, must be called in Privileged Mode
     *--------------------------------------*/
    MOV     r0, #0
    MCR     p15, 0, r0, c7, c5, 0
    /*--------------------------------------*
     * Flush DCache, must be called in Privileged Mode
     *--------------------------------------*/
    MOV     r0, #0
    MCR     p15, 0, r0, c7, c6, 0
    /*--------------------------------------*
     * Drain Write Buffer, must be called in Privileged mode
     *--------------------------------------*/
    MOV     r0, #0
    MCR     p15, 0, r0, c7, c10, 4
    MOV     pc, lr


/*---------------------------------------*
 * End of file
 *---------------------------------------*/
    .end