inits.s

source code of armboot for s3c4510

/*
 * File:    inita.s for Cygwin
 *
 * Purpose: Initialization procedure for CPU.
 */

#include "devicea.S"


#include "config.h"
#include "version.h"

/*----------------------  Stack Definition  ----------------------------*/
/***************************************************/
    .section .DataSeg_Stack, "aw", %nobits
/***************************************************/

// Stack memory section should starts immediately after the end of the
// BSS section
    .align

    .space  STACK_SIZE_UND
STACK_UND:
    .space  STACK_SIZE_ABT
STACK_ABT:
    .space  STACK_SIZE_IRQ
STACK_IRQ:
    .space  STACK_SIZE_FIQ
STACK_FIQ:
    .space  STACK_SIZE_USR
STACK_USR:
    .space  STACK_SIZE_SVC
STACK_SVC:




/*----------------------  Static Definitions  --------------------------*/

/*----------------------  Static Macros  -------------------------------*/

/*----------------------  Static Variables  ----------------------------*/
/***************************************************/
    .section .data, "aw"
/***************************************************/

/*----------------------  Export Variables  ----------------------------*/

/*----------------------  Export Functions  ----------------------------*/
    .global __main
    .global CPUS_u32GetCPSR
    .global CPUS_u32GetSP
    .global CPUS_vTrapKernelMode
    .global CPUS_u32GetMode
    .global MMUS_vCacheEnable
    .global MMUS_vCacheDisable

/*----------------------  Import Variables  ----------------------------*/
    .extern _text_base                  // Base of ROM code
    .extern _text_end                   // End of ROM code (=start of ROM data)
    .extern _data_base                  // Base of RAM to initialise
    .extern _data_end                   // End of RAM to initialise
    .extern _bss_base                   // Base of zero initialise RAM data
    .extern _bss_end                    // End of zero initialise RAM data

/*----------------------  Import Functions  ----------------------------*/
    .extern Main_Entry

    .extern EISR_ExcptHndlr_Undef
    .extern EISR_ExcptHndlr_Prefetch
    .extern EISR_ExcptHndlr_Abort
    .extern EISR_ExcptHndlr_Irq
    .extern EISR_ExcptHndlr_Fiq




/***************************************************/
    .section .CodeSeg_Init, "ax"
/***************************************************/

/*---------------------------------------*
 * Define entry point
 *---------------------------------------*/
__main:                                 // defined to ensure that C runtime system is not linked in



/*---------------------------------------*
 * (1). 1st Exception Handler Vector Entry Pointer (or setup vectors when ram at address 0)
 *---------------------------------------*/
    // Now fall into the instruction which will continue
    // execution at 'ExcptHndlr_System_Reset'
ExcptHndlr_Vector_Init:
    ADR     pc, ExcptHndlr_System_Reset // for warm reboot, use relative jump
    LDR     pc, Undefined_Addr
    LDR     pc, SWI_Addr
    LDR     pc, Prefetch_Addr
    LDR     pc, Abort_Addr
    LDR     pc, Reserv_Addr
    LDR     pc, IRQ_Addr
    LDR     pc, FIQ_Addr

Reset_Addr:     .long   ExcptHndlr_System_Reset
Undefined_Addr: .long   ExcptHndlr_System_Undefined
SWI_Addr:       .long   ExcptHndlr_System_Swi
Prefetch_Addr:  .long   ExcptHndlr_System_Prefetch
Abort_Addr:     .long   ExcptHndlr_System_Abort
Reserv_Addr:    .long   ExcptHndlr_System_Reserv
IRQ_Addr:       .long   ExcptHndlr_System_Irq
FIQ_Addr:       .long   ExcptHndlr_System_Fiq


SystemMemConRegInitData:
    .long   rB0CON      // EXT I/O Bank #0 Control Register
    .long   rB1CON      // EXT I/O Bank #1 Control Register
    .long   rB2CON      // EXT I/O Bank #2 Control Register
    .long   rB3CON      // EXT I/O Bank #3 Control Register
    .long   rB4CON      // EXT I/O Bank #4 Control Register
    .long   rB5CON      // EXT I/O Bank #5 Control Register
    .long   rB6CON      // EXT I/O Bank #6 Control Register
    .long   rB7CON      // EXT I/O Bank #7 Control Register
    .long   rMUXBCON    // Muxed bus Control Register
    .long   rWAITCON    // Wait Control Register


/*---------------------------------------*
 * (3). 3rd Exception Handler Vector Entry Pointer (Consist of function call to C-Program)
 *---------------------------------------*/
ExcptHndlr_System_Undefined:
    STMDB   sp!, {r0-r12,lr}
    MOV     r0, lr
    BL      EISR_ExcptHndlr_Undef
    LDMIA   sp!, {r0-r12,pc}^


ExcptHndlr_System_Swi:
    STMDB   sp!, {r0-r12,lr}
    LDR     r0, [lr, #-4]
    BIC     r0, r0, #0xFF000000
    CMP     r0, #0xFF
    BEQ     SwiCpuSetSVC
    CMP     r0, #0xFE
    BEQ     SwiCpuSetSYS
    LDMIA   sp!, {r0-r12,pc}^
// SWI 0xFF: set CPU mode remain at SVC mode even when return
SwiCpuSetSVC:
    MRS     r1, SPSR
    BIC     r1, r1, #MODE_MASK
    ORR     r2, r1, #SVC_MODE
    MSR     SPSR, r2
    LDMIA   sp!, {r0-r12,pc}^
// SWI 0xFE: set CPU mode remain at SYS mode even when return
SwiCpuSetSYS:
    MRS     r1, SPSR
    BIC     r1, r1, #MODE_MASK
    ORR     r2, r1, #SYS_MODE
    MSR     SPSR, r2
    LDMIA   sp!, {r0-r12,pc}^


ExcptHndlr_System_Prefetch:
    STMDB   sp!, {r0-r12,lr}
    MOV     r0, lr
    BL      EISR_ExcptHndlr_Prefetch
    LDMIA   sp!, {r0-r12,lr}
    SUBS    pc, lr, #4


ExcptHndlr_System_Abort:
    STMDB   sp!, {r0-r12,lr}
    MOV     r0, lr
    BL      EISR_ExcptHndlr_Abort
    LDMIA   sp!, {r0-r12,lr}
    SUBS    pc, lr, #8


ExcptHndlr_System_Reserv:
    B       ExcptHndlr_System_Reserv


ExcptHndlr_System_Irq:
    // PATCH ....
    STMDB   sp!, {r0}
    MRS     r0, SPSR
    TST     r0, #I_Bit                  // If I bit = 1 (disable IRQ), exit
    LDMIA   sp!, {r0}
    SUBNES  pc, lr, #4

    STMDB   sp!, {r0-r12,lr}
    BL      EISR_ExcptHndlr_Irq
    LDMIA   sp!, {r0-r12,lr}
    SUBS    pc, lr, #4


ExcptHndlr_System_Fiq:
    STMDB   sp!, {r0-r7,lr}
    BL      EISR_ExcptHndlr_Fiq
    LDMIA   sp!, {r0-r7,lr}
    SUBS    pc, lr, #4




/*---------------------------------------*
 * The Reset Entry Point
 *---------------------------------------*/
ExcptHndlr_System_Reset:


    MOV     r8, #0                      // To setup SWI exception table address
    ADRL    r9, ExcptHndlr_Vector_Init
                                        // before we call SWI
    LDMIA   r9!, {r0-r7}
    STMIA   r8!, {r0-r7}
    LDMIA   r9!, {r0-r7}
    STMIA   r8!, {r0-r7}

    SWI     0xFF                        // set CPU mode to SVC mode


    /*-----------------------------------*
     * disable IRQ/FIQ
     *-----------------------------------*/
    // when reset, should had been at this mode,
    // but we want to make sure
    MRS     r0, CPSR
    ORR     r0, r0, #IFRQ_DISABLE
    MSR     CPSR, r0

    /*-----------------------------------*
     * disable interrupt
     *-----------------------------------*/
    // CP15 Big Endian Set accoding to SYSCFG.big
    LDR     r1, =ASIC_SYS_SYSCFG
    LDR     r0, [r1]
    LDR     r2, =BIG
    ANDS    r0, r0, r2

    LDRNE   r0, =0x80
    MCRNE   p15, 0, r0, c1, c0, 0   // CP15 Big endiag setting

    // disable all interrupt
    LDR     r1, =ASIC_INT_INTMASK
    LDR     r0, =rINTMASK_ALL       // All Interrupt Disable
    STR     r0, [r1]

    LDR     r1, =ASIC_INT_EXTMASK
    LDR     r0, =rEXTMASK_ALL       // All Interrupt Disable
    STR     r0, [r1]

    // disable all PCI interrupt
    LDR     r1, =ASIC_PCI_PCIINTEN
    MOV     r0, #0
    STR     r0, [r1]

    // clear all PCI pending interrupt
    LDR     r1, =ASIC_PCI_PCIINTST
    LDR     r0, =rINTST_CLSALL
    STR     r0, [r1]


#if !defined(__SWITCH_CPUIF_PCI)
    /******************************************************
     * Initialize Memory Controller for EXT I/O Bank1(switch)
     ******************************************************/
    LDR     r1, =ASIC_EIO_B1CON
    LDR     r0, =rB1CON
    STR     r0, [r1]

    LDR     r1, =ASIC_EIO_WAITCON