📄 devicea.s
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/*
* File: devicea.S for cygwin
*/
/*************************************************************************/
/* Format of the Program Status Register */
/*************************************************************************/
/* */
/* 31 30 29 28 7 6 5 4 3 2 1 0 */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
/*| N | Z | C | V | | I | F | T | M4 ~ M0 | */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
/* */
/* Processor Mode and Mask */
/* */
/*************************************************************************/
.equ FLAG_MASK, 0xF0000000 // Flag (NZCV) Bits Mask
.equ I_Bit, 0x80 // IRQ disable
.equ F_Bit, 0x40 // FIQ disable
.equ T_Bit, 0x20 // Thumb state, read only
.equ IFRQ_DISABLE, 0xC0 // Interrupt disable mask value
.equ IFRQ_ENABLE, 0x00 // Interrupt enable mask value
.equ IFRQ_MASK, 0xC0 // Interrupt lockout mask value
.equ UND_MODE, 0x1B // (UND) Undefine Mode
.equ ABT_MODE, 0x17 // (ABT) Abort Mode
.equ SVC_MODE, 0x13 // (SVC) Supervisor Mode
.equ IRQ_MODE, 0x12 // (IRQ) Interrupt Mode
.equ FIQ_MODE, 0x11 // (FIQ) Fast Interrupt Mode
.equ USR_MODE, 0x10 // (USR) User Mode
.equ SYS_MODE, 0x1F // (SYS) System Mode
.equ MODE_MASK, 0x1F // Processor Mode Mask
/*------------------------------------------------------*
* Memory area layout definition
*------------------------------------------------------*/
.equ ASIC_DRAM_BASE_ADDR, 0x00000000
.equ ASIC_VEC_TBL_BASE_ADDR, 0x00F00000 // limit addr of exception vector table
.equ ASIC_DRAM_SIZE, 0x01000000 // size == 8MB x 2 == 16MB
.equ ASIC_ROM_BASE_ADDR, 0x40000000 // it is the SDRAM bank0 before the remap, for CopyRomToRamLoop
.equ ASIC_ROM_0_SIZE, 0x00400000 // size == 4MB
.equ ASIC_ROM_1_SIZE, 0x00400000 // size == 4MB
// Although if when physically ROM0 is 512KB
// but we still configure it as 4MB anyway
.equ ASIC_EXTIO_BASE_ADDR, 0x81000000
.equ ASIC_SRAM_BASE_ADDR, 0x03FE0000 // Internal SRAM, size == 8KB
// If not use cache, then we could
// use the cache ram as internal sram
/*---------------------------------------*
* SYSTEM STACK MEMORY
*---------------------------------------*/
.equ STACK_SIZE_UND, 512
.equ STACK_SIZE_ABT, 512
.equ STACK_SIZE_IRQ, 4096
.equ STACK_SIZE_FIQ, 512
.equ STACK_SIZE_SVC, 2048
.equ STACK_SIZE_USR, 65536
.equ MHz, 1000000
.equ fMCLK, (133*MHz) // Fixed System CLOCK
/*------------------------------------------------------*
* SPECIAL REGISTERS : Start Address After System Reset
*------------------------------------------------------*/
.equ ASIC_SOC_BASE_ADDR, 0xF0000000
/*------------------------------------------------------*
* System Configuration Special Register
*------------------------------------------------------*/
.equ ASIC_SYS_SYSCFG, ASIC_SOC_BASE_ADDR + 0x0000
.equ CPLLREN, (0x1 << 31) // CPLLCON Enable 0 : Pin cfg. 1 : Reg cfg.
.equ SPLLREN, (0x1 << 30) // SPLLCON Enable 0 : Pin cfg. 1 : Reg cfg.
.equ UPLLREN, (0x1 << 29) // UPLLCON Enable 0 : Pin cfg. 1 : Reg cfg.
.equ PPLLREN, (0x1 << 28) // PPLLCON Enable 0 : Pin cfg. 1 : Reg cfg.
.equ CPLLFD, (0x1 << 27) // Core Clock 0 : Disable 1 : Enable during the configuration.
.equ SPLLFD, (0x1 << 26) // System Clock 0 : Disable 1 : Enable during the configuration.
.equ UPLLFD, (0x1 << 25) // USB Clock 0 : Disable 1 : Enable during the configuration.
.equ PPLLFD, (0x1 << 24) // Core Clock 0 : Disable 1 : Enable during the configuration.
.equ BIG, (0x1 << 16) // (Read only)0 : Little endian 1: Big endian
.equ REMAP, (0x1 << 8) // 0 : REMAP Disable | 1: REMAP Enable
// ---------------------------------------------------
// ROM Bank0 : 0x00000000 | ROM Bank0 : 0x80000000
// ROM Bank1 : 0x01000000 | ROM Bank1 : 0x81000000
// ROM Bank7 : 0x07000000 | ROM Bank7 : 0x87000000
// SDRAM Bank0 : 0x40000000 | SDRAM Bank0 : 0x00000000
// SDRAM Bank1 : 0x80000000 | SDRAM Bank1 : 0x40000000
.equ HCLKO_DIS, (0x1 << 4) // HCLKO output disable
// 1'b0 = HCLKO Always Enable
// 1'b1 = HCLKO Enable Only when SDRAM access
.equ ARB, (0x0 << 0) // System bus arbitration 0 : round robbin, 1: Fixed priority
.equ rSYSCFG, ARB
/*------------------------------------------------------*
* Ext. I/O Bank Controller Special Registers
*------------------------------------------------------*/
.equ ASIC_EIO_B0CON, ASIC_SOC_BASE_ADDR + 0x10000 // Bank 0 control register
.equ DataWidth0, (2 << 30) // 0=Reserved,1=8it, 2=16bit, 3=32bit read only BOSIZE[1:0]
.equ PageMode0, (0 << 28) // 0=Normal ROM or External I/O 1=4word 2=8word 3=16word
.equ BankSize0, (3 << 24) // 0=Disable 1=1M 2=2M 3=4M 4=8M 5=16M
.equ IS0, (0 << 23) // 0 = nWBE function, 1 = nBE function
.equ TACC0, (0x9 << 16) // 0x3 = 3cycles, 0x4 = 4cycles, 0x5 = 5cycles, 0x6 = 6cycles, 0x7 = 7cycles
// 0x8 = 8cycles, 0x9 = 9cycles, 0xA =10cycles, 0xB =11cycles, 0xC =12cycles
// 0xD =13cycles, 0xE =14cycles, 0xF =15cycles, 0x10=16cycles, 0x11=17cycles
// 0x12=18cycles, 0x13=19cycles, 0x14=20cycles, 0x15=21cycles, 0x16=22cycles
// 0x17=23cycles, 0x18=24cycles, 0x19=25cycles, 0x1A=26cycles, 0x1B=27cycles
// 0x1C=28cycles, 0x1D=29cycles, 0x1E=30cycles, 0x1F=31cycles
.equ TPA0, (0xe << 12) // 0x1 = 1cycles, 0x2 = 2cycles ~ 0xF =15cycles
.equ TACS0, (0x9 << 8) // 0x1 = 1cycles, 0x2 = 2cycles ~ 0xF =15cycles
.equ TCOS0, (0x3 << 4) // 0x1 = 1cycles, 0x2 = 2cycles ~ 0xF =15cycles
.equ TCOH0, (0x6 << 0) // 0x1 = 1cycles, 0x2 = 2cycles ~ 0xF =15cycles
.equ rB0CON, 0x8314E488 // DataWidth0+PageMode0+BankSize0+IS0+TACC0+TPA0+TACS0+TCOS0+TCOH0
.equ ASIC_EIO_B1CON, ASIC_SOC_BASE_ADDR + 0x10004 // Bank 1 control register
.equ DataWidth1, (2 << 30)
.equ PageMode1, (0 << 28)
.equ BankSize1, (0x1 << 24)
.equ IS1, (0 << 23)
.equ TACC1, (0xf << 16)
.equ TPA1, (0x0 << 12)
.equ TACS1, (0x3 << 8)
.equ TCOS1, (0x1 << 4)
.equ TCOH1, (0x2 << 0)
.equ rB1CON, DataWidth1+PageMode1+BankSize1+IS1+TACC1+TPA1+TACS1+TCOS1+TCOH1
.equ ASIC_EIO_B2CON, ASIC_SOC_BASE_ADDR + 0x10008 // Bank 2 control register
.equ DataWidth2, (2 << 30)
.equ PageMode2, (0 << 28)
.equ BankSize2, (3 << 24)
.equ IS2, (0 << 23)
.equ TACC2, (0x9 << 16)
.equ TPA2, (0xe << 12)
.equ TACS2, (0x9 << 8)
.equ TCOS2, (0x3 << 4)
.equ TCOH2, (0x6 << 0)
.equ rB2CON, DataWidth2+PageMode2+BankSize2+IS2+TACC2+TPA2+TACS2+TCOS2+TCOH2
.equ ASIC_EIO_B3CON, ASIC_SOC_BASE_ADDR + 0x1000C // Bank 3 control register
.equ DataWidth3, (2 << 30)
.equ PageMode3, (0 << 28)
.equ BankSize3, (3 << 24)
.equ IS3, (0 << 23)
.equ TACC3, (0x9 << 16)
.equ TPA3, (0xe << 12)
.equ TACS3, (0x9 << 8)
.equ TCOS3, (0x3 << 4)
.equ TCOH3, (0x6 << 0)
.equ rB3CON, DataWidth3+PageMode3+BankSize3+IS3+TACC3+TPA3+TACS3+TCOS3+TCOH3
.equ ASIC_EIO_B4CON, ASIC_SOC_BASE_ADDR + 0x10010 // Bank 4 control register
.equ DataWidth4, (2 << 30)
.equ PageMode4, (0 << 28)
.equ BankSize4, (3 << 24)
.equ IS4, (0 << 23)
.equ TACC4, (0x9 << 16)
.equ TPA4, (0xe << 12)
.equ TACS4, (0x9 << 8)
.equ TCOS4, (0x3 << 4)
.equ TCOH4, (0x6 << 0)
.equ rB4CON, DataWidth4+PageMode4+BankSize4+IS4+TACC4+TPA4+TACS4+TCOS4+TCOH4
.equ ASIC_EIO_B5CON, ASIC_SOC_BASE_ADDR + 0x10014 // Bank 5 control register
.equ DataWidth5, (2 << 30)
.equ PageMode5, (0 << 28)
.equ BankSize5, (3 << 24)
.equ IS5, (0 << 23)
.equ TACC5, (0x9 << 16)
.equ TPA5, (0xe << 12)
.equ TACS5, (0x9 << 8)
.equ TCOS5, (0x3 << 4)
.equ TCOH5, (0x6 << 0)
.equ rB5CON, DataWidth5+PageMode5+BankSize5+IS5+TACC5+TPA5+TACS5+TCOS5+TCOH5
.equ ASIC_EIO_B6CON, ASIC_SOC_BASE_ADDR + 0x10018 // Bank 6 control register
.equ DataWidth6, (2 << 30)
.equ PageMode6, (0 << 28)
.equ BankSize6, (3 << 24)
.equ IS6, (0 << 23)
.equ TACC6, (0x9 << 16)
.equ TPA6, (0xe << 12)
.equ TACS6, (0x9 << 8)
.equ TCOS6, (0x3 << 4)
.equ TCOH6, (0x6 << 0)
.equ rB6CON, DataWidth6+PageMode6+BankSize6+IS6+TACC6+TPA6+TACS6+TCOS6+TCOH6
.equ ASIC_EIO_B7CON, ASIC_SOC_BASE_ADDR + 0x1001C // Bank 7 control register
.equ DataWidth7, (2 << 30)
.equ PageMode7, (0 << 28)
.equ BankSize7, (3 << 24)
.equ IS7, (0 << 23)
.equ TACC7, (0x9 << 16)
.equ TPA7, (0xe << 12)
.equ TACS7, (0x9 << 8)
.equ TCOS7, (0x3 << 4)
.equ TCOH7, (0x6 << 0)
.equ rB7CON, DataWidth7+PageMode7+BankSize7+IS7+TACC7+TPA7+TACS7+TCOS7+TCOH7
.equ ASIC_EIO_MUXBCON, ASIC_SOC_BASE_ADDR + 0x10020 // Muxed bus control register
.equ MBE7, 0x0 << 31 // 0x0=disable, 0x1=enable
.equ MBE6, 0x0 << 30
.equ MBE5, 0x0 << 29
.equ MBE4, 0x0 << 28
.equ MBE3, 0x0 << 27
.equ MBE2, 0x0 << 26
.equ MBE1, 0x0 << 25
.equ MBE0, 0x0 << 24
.equ TMA7, 0x3 << 21 // 0x1=1cycle, 0x2=2cycle, 0x3=3cycle,..,0x7=7cycle,0x0=8cycle
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