devicea.s

source code of armboot for s3c4510

.equ    TMA6,               0x3 << 18
.equ    TMA5,               0x3 << 15
.equ    TMA4,               0x3 << 12
.equ    TMA3,               0x3 << 9
.equ    TMA2,               0x3 << 6
.equ    TMA1,               0x3 << 3
.equ    TMA0,               0x3 << 0

.equ    ALLMUXEN,           (0xff << 24)
.equ    ALLMUXDIS,          (0x0 << 0)

.equ    rMUXBCON,           MBE7+MBE6+MBE5+MBE4+MBE3+MBE2+MBE1+MBE0+TMA7+TMA6+TMA5+TMA4+TMA3+TMA2+TMA1+TMA0


.equ    ASIC_EIO_WAITCON,   ASIC_SOC_BASE_ADDR + 0x10024    // Wait control register
.equ    COHDIS7,            0x1 << 23   // This forces TCOH to '0' for read to read, write to write,
                                        // and write to read access in bank 7
.equ    COHDIS6,            0x1 << 22   // 0: disable  1: enable
.equ    COHDIS5,            0x1 << 21
.equ    COHDIS4,            0x1 << 20
.equ    COHDIS3,            0x1 << 19
.equ    COHDIS2,            0x1 << 18
.equ    COHDIS1,            0x1 << 17
.equ    COHDIS0,            0x1 << 16

.equ    EWAITEN7,           0x0 << 15   // External wait enable for bank(n) 0 : disable,  1 : enable
.equ    EWAITEN6,           0x0 << 14
.equ    EWAITEN5,           0x0 << 13
.equ    EWAITEN4,           0x0 << 12
.equ    EWAITEN3,           0x0 << 11
.equ    EWAITEN2,           0x0 << 10
.equ    EWAITEN1,           0x0 << 9
.equ    EWAITEN0,           0x0 << 8

.equ    NREADY7,            0x0 << 7    // nWait / nReady select for bank(n) 0 = nWait,   1 = nReady
.equ    NREADY6,            0x0 << 6
.equ    NREADY5,            0x0 << 5
.equ    NREADY4,            0x0 << 4
.equ    NREADY3,            0x0 << 3
.equ    NREADY2,            0x0 << 2
.equ    NREADY1,            0x0 << 1
.equ    NREADY0,            0x0 << 0

.equ    rCOHDIS,            COHDIS7+COHDIS6+COHDIS5+COHDIS4+COHDIS3+COHDIS2+COHDIS1+COHDIS0

.equ    rEWAITEN,           EWAITEN7+EWAITEN6+EWAITEN5+EWAITEN4+EWAITEN3+EWAITEN2+EWAITEN1+EWAITEN0
.equ    rNREADY,            NREADY7+NREADY6+NREADY5+NREADY4+NREADY3+NREADY2+NREADY1+NREADY0
.equ    rWAITCON,           rCOHDIS+rEWAITEN+rNREADY

.equ    ASIC_EIO_WDSCON,    ASIC_SOC_BASE_ADDR + 0x10028    // Wait data setup cycle control register

/*------------------------------------------------------*
 * SDRAM Special Registers
 *------------------------------------------------------*/
.equ    ASIC_SDRAM_CFGREG,  ASIC_SOC_BASE_ADDR + 0x20000

.equ    ExtBusWidth,        (0x0 << 0)  // 0x0=32bit,  0x1=16it
.equ    AutoPrecharg,       (0x0 << 1)  // 0x0=Auto Pre-charge,    0x1=No Auto Pre-charge
.equ    CASLatency,         (0x3 << 2)  // 0x0=Reserved 0x1=1cycle, 0x2=2cycles, 0x3=3cycles
.equ    Bank0Density,       (0x1 << 4)  // 0x0=16Mbit,  0x1=64Mbit, 0x2=128Mbit, 0x3=256Mbit
.equ    Bank1Density,       (0x1 << 6)  // 0x0=16Mbit,  0x1=64Mbit, 0x2=128Mbit, 0x3=256Mbit
// Optimized value
.equ    RowPrecharge,       (0x2 << 8)  // 0x0=1cycle   0x1=2cycle, 0x2=3cycles, 0x3=4cycles
.equ    RAStoCASdelay,      (0x2 << 10) // 0x0=1cycle   0x1=2cycle, 0x2=3cycles, 0x3=4cycles
.equ    RowCycle,           (0x8 << 12) // 0x0=1cycle   0x1=2cycle  ~  0xf=16cycles
.equ    RowActTime,         (0x5 << 16) // 0x0=1cycle   0x1=2cycle  ~  0xf=16cycles

.equ    rCFGREG,            ExtBusWidth+AutoPrecharg+CASLatency+Bank0Density+Bank1Density+RowPrecharge+RAStoCASdelay+RowCycle+RowActTime

.equ    ASIC_SDRAM_CMDREG,  ASIC_SOC_BASE_ADDR + 0x20004

.equ    INITS,              (0x0 << 0)  // Control bits for SDRAM Device initialization
                                        // 0x0=Normal operation 0x3=Reserved
                                        // 0x1=Auto issue a PALL to the SDRAM
                                        // 0x2=Auto issue a MRS  tot the SDRAM
.equ    NORMAL,             (0x0 << 0)
.equ    PALL,               (0x1 << 0)
.equ    MRS,                (0x2 << 0)

.equ    WBUF,               (0x1 << 2)  // Write Buffer Enable
                                        // 0x0=Merging Write buffer disable
                                        // 0x1=Merging Write buffer enable

.equ    rCMDREG,            INITS+WBUF


.equ    ASIC_SDRAM_REFREG,  ASIC_SOC_BASE_ADDR + 0x20008
                                        // Refresh =   (15.6*(fMCLK/MHz))
                                        // CMDREG = (fMCLK/MHz)*15 + (6*(fMCLK/MHz))/10
                                        // Clock >= 64/(15.6*Mhz) = 4.3Mh
                                        // Common refresh time period of 15.6us , SYSTEM CLK 66Mhz
                                        // 15.6Mhz X 66Mhz = 1029  refresh time

.equ    ASIC_SDRAM_WBTOREG, ASIC_SOC_BASE_ADDR + 0x2000C
.equ    rWBTOREG,           0x0


/*------------------------------------------------------*
 * PCI (Mini-PCI) & PC Card Controller
 *------------------------------------------------------*/
.equ    ASIC_PCI_PCIINTEN,  ASIC_SOC_BASE_ADDR + 0x110108
.equ    ASIC_PCI_PCIINTST,  ASIC_SOC_BASE_ADDR + 0x11010C

.equ    rINTST_CLSALL,      0xFFFFFFFF


/*------------------------------------------------------*
 * Interrupt Control Registers, 30 Internal Interrupt Sources, 6 External Interrupt Sources
 *------------------------------------------------------*/

.equ    ASIC_INT_INTMOD,    ASIC_SOC_BASE_ADDR + 0x140000
.equ    ASIC_INT_EXTMOD,    ASIC_SOC_BASE_ADDR + 0x140004
.equ    ASIC_INT_INTMASK,   ASIC_SOC_BASE_ADDR + 0x140008
.equ    ASIC_INT_EXTMASK,   ASIC_SOC_BASE_ADDR + 0x14000C

// Internal Interrupt vector for each device
.equ    INT_OFFSET_NOINT,   36

.equ    VEC_WDT_INT,        29
.equ    VEC_TMR5_INT,       28
.equ    VEC_TMR4_INT,       27
.equ    VEC_TMR3_INT,       26
.equ    VEC_TMR2_INT,       25
.equ    VEC_TMR1_INT,       24
.equ    VEC_TMR0_INT,       23
.equ    VEC_GDMA5_INT,      22
.equ    VEC_GDMA4_INT,      21
.equ    VEC_GDMA3_INT,      20
.equ    VEC_GDMA2_INT,      19
.equ    VEC_GDMA1_INT,      18
.equ    VEC_GDMA0_INT,      17
.equ    VEC_DES_INT,        16
.equ    VEC_EMC1_RX_INT,    15
.equ    VEC_EMC1_TX_INT,    14
.equ    VEC_EMC0_RX_INT,    13
.equ    VEC_EMC0_TX_INT,    12
.equ    VEC_SAR_ERROR_INT,  11
.equ    VEC_SAR_DONE_INT,   10
.equ    VEC_PCI_H_INT,      9
.equ    VEC_USB_F_INT,      8
.equ    VEC_USB_H_INT,      7
.equ    VEC_CUART_RX_INT,   6
.equ    VEC_CUART_TX_INT,   5
.equ    VEC_HUART1_RX_INT,  4
.equ    VEC_HUART1_TX_INT,  3
.equ    VEC_HUART0_RX_INT,  2
.equ    VEC_HUART0_TX_INT,  1
.equ    VEC_I2C_INT,        0

.equ    rINTMASK_ALL,       0x3FFFFFFF

// Internal Interrupt vector for each device
.equ    VEC_EXT5_INT,       5
.equ    VEC_EXT4_INT,       4
.equ    VEC_EXT3_INT,       3
.equ    VEC_EXT2_INT,       2
.equ    VEC_EXT1_INT,       1
.equ    VEC_EXT0_INT,       0

.equ    rEXTMASK_ALL,       0x8000003F

.equ    ASIC_INT_IPRIORHI,  ASIC_SOC_BASE_ADDR + 0x140010
.equ    ASIC_INT_IPRIORLO,  ASIC_SOC_BASE_ADDR + 0x140014
.equ    ASIC_INT_OFFSET_FIQ, ASIC_SOC_BASE_ADDR + 0x140018
.equ    ASIC_INT_OFFSET_IRQ, ASIC_SOC_BASE_ADDR + 0x14001C


/*-----------------------------------*
 * Definition of CP15/MMU register
 *-----------------------------------*/
.equ    MMU_PROTECT_ENABLE, (0x01 << 0)
.equ    MMU_DCACHE_ENABLE,  (0x01 << 2)
.equ    MMU_ICACHE_ENABLE,  (0x01 << 12)
.equ    MMU_REGION0_ENABLE, (0x01 << 0)
.equ    MMU_REGION1_ENABLE, (0x01 << 1)
.equ    MMU_REGION2_ENABLE, (0x01 << 2)
.equ    MMU_REGION3_ENABLE, (0x01 << 3)
.equ    MMU_REGION4_ENABLE, (0x01 << 4)
.equ    MMU_REGION5_ENABLE, (0x01 << 5)
.equ    MMU_REGION6_ENABLE, (0x01 << 6)
.equ    MMU_REGION7_ENABLE, (0x01 << 7)

.equ    MMU_PRIV_NONE,      (0x00)
.equ    MMU_PRIV_PRIV_ONLY, (0x01)
.equ    MMU_PRIV_USR_READ,  (0x02)
.equ    MMU_PRIV_FULL,      (0x03)
.equ    MMU_SIZE_4K,        ((12 - 1) << 1) // 2 ^1 2 = 4   KB
.equ    MMU_SIZE_8KB,       ((13 - 1) << 1) // 2 ^ 13 = 8   KB
.equ    MMU_SIZE_16KB,      ((14 - 1) << 1) // 2 ^ 14 = 16  KB
.equ    MMU_SIZE_32KB,      ((15 - 1) << 1) // 2 ^ 15 = 32  KB
.equ    MMU_SIZE_64KB,      ((16 - 1) << 1) // 2 ^ 16 = 64  KB
.equ    MMU_SIZE_128KB,     ((17 - 1) << 1) // 2 ^ 17 = 128 KB
.equ    MMU_SIZE_256KB,     ((18 - 1) << 1) // 2 ^ 18 = 256 KB
.equ    MMU_SIZE_512KB,     ((19 - 1) << 1) // 2 ^ 19 = 512 KB
.equ    MMU_SIZE_1MB,       ((20 - 1) << 1) // 2 ^ 20 = 1   MB
.equ    MMU_SIZE_2MB,       ((21 - 1) << 1) // 2 ^ 21 = 2   MB
.equ    MMU_SIZE_4MB,       ((22 - 1) << 1) // 2 ^ 22 = 4   MB
.equ    MMU_SIZE_8MB,       ((23 - 1) << 1) // 2 ^ 23 = 8   MB
.equ    MMU_SIZE_16MB,      ((24 - 1) << 1) // 2 ^ 24 = 16  MB
.equ    MMU_SIZE_32MB,      ((25 - 1) << 1) // 2 ^ 25 = 32  MB
.equ    MMU_SIZE_64MB,      ((26 - 1) << 1) // 2 ^ 26 = 64  MB
.equ    MMU_SIZE_128MB,     ((27 - 1) << 1) // 2 ^ 27 = 128 MB
.equ    MMU_SIZE_256MB,     ((28 - 1) << 1) // 2 ^ 28 = 256 MB
.equ    MMU_SIZE_512MB,     ((29 - 1) << 1) // 2 ^ 29 = 512 MB
.equ    MMU_SIZE_1GB,       ((30 - 1) << 1) // 2 ^ 30 = 1   GB
.equ    MMU_SIZE_2GB,       ((31 - 1) << 1) // 2 ^ 31 = 2   GB
.equ    MMU_SIZE_4GB,       ((32 - 1) << 1) // 2 ^ 32 = 4   GB


/*-----------------------------------*
 * Region Base, Size definition
 *-----------------------------------*/
.equ    MMU_RAM_BASE,        0x00000000      // 0 ~ 8  MB = Code/Data
.equ    MMU_DMA_BASE,        0x00800000      // 8 ~ 16 MB , Uncachable
.equ    MMU_ROM_BASE,        0x80000000      // 2GB = System ROM
.equ    MMU_PCI_BASE,        0xC0000000      // PCI Space
.equ    MMU_SOC_BASE,        ASIC_SOC_BASE_ADDR
.equ    MMU_EXT_BASE,        ASIC_EXTIO_BASE_ADDR

.equ    MMU_REGION0,         (MMU_RAM_BASE | MMU_SIZE_8MB    | 1)
.equ    MMU_REGION1,         (MMU_DMA_BASE | MMU_SIZE_8MB    | 1)
.equ    MMU_REGION2,         (MMU_ROM_BASE | MMU_SIZE_4MB    | 1)
.equ    MMU_REGION3,         (MMU_PCI_BASE | MMU_SIZE_512MB  | 1)
.equ    MMU_REGION4,         (MMU_SOC_BASE | MMU_SIZE_256MB  | 1)
.equ    MMU_REGION5,         (MMU_EXT_BASE | MMU_SIZE_64KB   | 1)
.equ    MMU_REGION6,         0
.equ    MMU_REGION7,         0