start.s

source code of armboot for s3c4510

	 * nTIMER4_INT (36), nTIMER5_INT (37), nWATCHDOG_INT (38)
	 */

	ldr		r0, =TIMER_TIC
	ldr		r1, =0x7f
	str		r1, [r0, #0]

	mov		pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */
MEMCON_INITTBL:
	.word 	rB0CON			/* EXT I/O Bank #0 Control Register */
	.word 	rB1CON			/* EXT I/O Bank #1 Control Register */		
	.word 	rB2CON			/* EXT I/O Bank #2 Control Register */
	.word 	rB3CON			/* EXT I/O Bank #3 Control Register */
	.word 	rB4CON			/* EXT I/O Bank #4 Control Register */
	.word 	rB5CON			/* EXT I/O Bank #5 Control Register */
	.word 	rB6CON			/* EXT I/O Bank #6 Control Register */
	.word 	rB7CON			/* EXT I/O Bank #7 Control Register */
	.word 	rMUXBCON		/* Muxed bus Control Register */
	.word 	rWAITCON		/* Wait Control Register */
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add     r8, sp, #S_PC

	ldr	r2, _armboot_end
	add	r2, r2, #CONFIG_STACKSIZE
	sub	r2, r2, #8
	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add     r8, sp, #S_PC
	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
	str     lr, [r8, #0]                    @ Save calling PC
	mrs     r6, spsr
	str     r6, [r8, #4]                    @ Save CPSR
	str     r0, [r8, #8]                    @ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, _armboot_end		@ setup our mode stack
	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
	sub	r13, r13, #8

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str     lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	msr	spsr_c, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl 	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl 	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl 	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl 	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl 	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl 	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl 	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl 	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl 	do_fiq

#endif

	.align	5


@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@ CACHE Setting    choish 20020827
.global _ICache_Enable
_ICache_Enable:
		mrc	15, 0, r0, c1, c0, 0
		orr	r0, r0, #0x1000
		mcr	15, 0, r0, c1, c0, 0
		mov	pc, lr


		.global _ICache_Disable
_ICache_Disable:
		mrc	15, 0, r0, c1, c0, 0
		bic	r0, r0, #0x1000
		mcr	15, 0, r0, c1, c0, 0
		mov	pc, lr

		.global _ICache_Flush
_ICache_Flush:
		mov	r0, #0
		mcr	15, 0, r0, c7, c5, 0
		mov	pc, lr

		.global _ICache_Flush_Single
_ICache_Flush_Single:
		mov	r0, r0, lsl #4	@ Segment
		mov	r1, r1, lsl #26	@ Line
		orr	r0, r0, r1
		mcr	15, 0, r0, c7, c5, 2
		mov	pc, lr
		
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ DCache
		.global _DCache_Enable
_DCache_Enable:
		mrc	15, 0, r0, c1, c0, 0
		orr	r0, r0, #0x4
		mcr	15, 0, r0, c1, c0, 0
		mov	pc, lr

		.global _DCache_Disable
_DCache_Disable:
		mrc	15, 0, r0, c1, c0, 0
		bic	r0, r0, #0x4
		mcr	15, 0, r0, c1, c0, 0
		mov	pc, lr

		.global _DCache_Flush
_DCache_Flush:
		mov	r0, #0
		mcr	15, 0, r0, c7, c6, 0
		mov	pc, lr

		.global _DCache_Flush_Single
_DCache_Flush_Single:
		mov	r0, r0, lsl #4	@ Segment
		mov	r1, r1, lsl #26	@ Line
		orr	r0, r0, r1
		mcr	15, 0, r0, c7, c6, 2
		mov	pc, lr

		.global _DCache_Clean_Single
_DCache_Clean_Single:
		mov	r0, r0, lsl #4	@ Segment
		mov	r1, r1, lsl #26	@ Line
		orr	r0, r0, r1
		mcr	15, 0, r0, c7, c10, 2
		mov	pc, lr

		.global _DCache_CFlush_Single	@ Clean & flush
_DCache_CFlush_Single:
		mov	r0, r0, lsl #4	@ Segment
		mov	r1, r1, lsl #26	@ Line
		orr	r0, r0, r1
		mcr	15, 0, r0, c7, c14, 2
		mov	pc, lr

		.global _DCache_CFlush
_DCache_CFlush:
		stmfd	sp!, {r1,r2}
		mov	r1, #0
1:		mov	r0, #0
2:		orr	r2, r1, r0
		mcr	15, 0, r0, c7, c14, 2
		add	r0, r0, #0x10
		cmp	r0, #0x40
		bne	2b
		add	r1, r1, #0x04000000
		cmp	r1, #0
		bne	1b
		ldmfd	sp!, {r1,r2}
		mov	pc, lr
		
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ Write Buffer WB
@ 		void	_WB_Enable (int region);

		.global _WB_Enable
_WB_Enable:	stmfd	sp!, {r1,r2}
		mrc	15, 0, r1, cr3, cr0, 0
		mov	r2, #1
		orr	r1, r1, r2, lsl r0
		mcr	15, 0, r1, cr3, cr0, 0
		ldmfd	sp!, {r1,r2}
		mov	pc, lr

@ 		void	_WB_Disable (int region);

		.global _WB_Disable
_WB_Disable:	stmfd	sp!, {r1,r2}
		mrc	15, 0, r1, cr3, cr0, 0
		mov	r2, #1
		bic	r1, r1, r2, lsl r0
		mcr	15, 0, r1, cr3, cr0, 0
		ldmfd	sp!, {r1,r2}
		mov	pc, lr

		.global _WB_Drain
_WB_Drain:	mov	r0, #0
		mcr	15, 0, r0, cr7, cr10, 4
		mov	pc, lr
		


@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@ Protection Unit setting  choish 20020827

.globl reset_cpu
reset_cpu:
@@@@@@@@@@@@@@@@@@@@@@@
@ instruction region set
	ldr	R1, =0x0000003F	 	@ code  region 0 4Gbyte - background
	MCR	p15, 0, R1, c6, c0, 1
	ldr	R1, =0x00000031		@ code	region 1 32MB - SDRAM
	MCR p15, 0, R1, c6, c1, 1	


@@@@@@@@@@@@@@@@@@@@@@@
@ data region set
	ldr	R1, =0x0000003F	 	@ data  region 0 4Gbyte - background
	MCR	p15, 0, R1, c6, c0, 0
	@ldr	R1, =0x80000029 	@ data  region 1 2MB - Flash
	@MCR	p15, 0, R1, c6, c1, 0
	@ldr	R1, =0x83000027		@ data	region 2 1MB - SRAM
	@MCR p15, 0, R1, c6, c2, 0
	ldr	R1, =0x00000031		@ data	region 1 32MB - SDRAM
	MCR p15, 0, R1, c6, c1, 0	
@	ldr	R1, =0x01E00029		@ data	region 2 2MB - SDRAM
@	MCR p15, 0, R1, c6, c2, 0
	ldr	R1, =0x0180002D		@ data	region 2 8MB - SDRAM
	MCR p15, 0, R1, c6, c2, 0

	
	mov	R1, #0x2		@ code Region Cachable bit setting
	MCR	p15, 0, R1, c2, c0, 1
	@ 1 cachable
	mov	R1, #0x2		@ data Region Cachable bit setting
	MCR	p15, 0, R1, c2, c0, 0
	@  1 cachable

	mov	R1, #0x4		@ Write Buffer Region setting
	MCR	p15, 0, R1, c3, c0, 0 @ DMA access region select
	
	ldr	R1,=0xfff
	MCR     p15,0,R1,c5,c0,1   	@ enable full access on Inst Region 0-5
	MCR     p15,0,R1,c5,c0,0   	@ enable full access on Data Region 0-5

	MRC	p15, 0, r0, c1, c0	@ get control register
	orr	r0, r0, #1		@ Enable PU
	ldr	r1, =0x3fffcf02		@ all "SB0"
	bic	r0, r0, r1
	orr	r0, r0, #0x0078		@ all "SB1"
	bic	r0, r0, #0x2000		@ No alternate vectors
	bic	r0, r0, #0x0080		@ Little-endian
	orr	r0, r0, #0x0004		@ disable DCache
	orr	r0, r0, #0x1000		@ Enable ICache
@	and	r0, r0, #0x3fffffff	@ Set Fast bus mode	@ Impossible to set bus mode !?
	orr	r0, r0, #0xC0000000	@ Set Async bus mode
	
	MCR     p15,0,R0,c1,c0,0
	
	nop;nop;nop
	mov	pc, lr

/*
 *************************************************************************
 *
 * Below is for connection with uClinux environment.
 * And, 
 *
 *************************************************************************
 */
#ifdef CONFIG_UCBOOTSTRAP

	    .global	UndInstr
UndInstr:
	    str		r6, PtTmp	@ save r6 & r7
	    str		r7, PtTmp+4
	    ldr		r6, [lr, #-4]	@ get code of undef instr
	    ldr		r7, =0xe65a4f10	@ bootstrap magic number
	    cmp		r6, r7			@ is it bootstrap syscall
	    ldral	r6, PtTmp		@ restore r6 & r7
	    ldral	r7, PtTmp+4
	    beq		.+12

	    @---------------------------< Kernel undefined instr >
	    mov		pc, $0xe4	@ 0xe4 is a kernel-2.0 vector_undefinstr addres.
	    nop				@ For compability it is still here for kernel-2.4.
	    nop				@ But to make it work the following was done :
	    nop				@ 1. from this address to the 0x200 (kernel __stub_start)
					@    memory was fillout by "nop" instructions.
					@ 2. in the kernel-2.4 the vector_undefinstr was moved to
					@    the __stub_start.
	    
	    @---------------------------< Bootstrap system call >
@ hans, changed stack area to 0x4000 ( empty area in .text, see system.map file )
@<--
@	    ldr		sp, =0x00800000	@ Bootstrap stack pointer
@-->
	    ldr		sp, =0x4000	@ Bootstrap stack pointer
@-->

	    stmfd	sp, {lr}	@ save return register
	    sub		sp, sp, #4
	    stmfd	sp, {r0-r12}	@ save work registers
	    sub		sp, sp, #52
	    ldr		r6, PtCallTable @ r6 <- function table address
	    str		r4, [sp, #-4]!	@ push r4->sp 5th argument
	    mov		lr, pc		@ save return address	
	    ldr		pc, [r6, r10, lsl #2] @ bootstrap syscall
	    add		sp, sp, #8	
	    ldmfd	sp, {r1-r12}	@ restore work reg without R0
	    add		sp, sp, #48
	    ldmfd	sp, {pc}^	@ return 

@--------------------------------------------------------------	    
	    .global	bsc_nullsyscall
bsc_nullsyscall:
	    mov		pc, lr	    

@--------------------------------------------------------------
		.global go2
go2:		mov	pc, r0
		nop

@--------------------------------------------------------------
PtCallTable:
                                /* not implemented */
        .word   .+4
        .word   bsc_reset       @ bsc_reset         @ 0
        .word   bsc_test                            @ 1
        .word   bsc_nullsyscall                     @ 2
        .word   bsc_nullsyscall                     @ 3
        .word   bsc_nullsyscall @ bsc_program           @ 4
        .word   bsc_nullsyscall                     @ 5
        .word   bsc_nullsyscall                     @ 6
        .word   bsc_nullsyscall                     @ 7
        .word   bsc_nullsyscall                     @ 8
        .word   bsc_nullsyscall                     @ 9
        .word   bsc_nullsyscall                     @ 10
        .word   bsc_nullsyscall                     @ 11
        .word   bsc_gethwaddr                       @ 12
        .word   bsc_getserialnum                    @ 13
        .word   bsc_getenv                      @ 14
        .word   bsc_setenv                      @ 15
        .word   bsc_setpmask                        @ 16
        .word   bsc_readenv @ bsc_readenv           @ 17
        .word   flash_chattr_range @ flash_chattr_range @ 18
        .word   flash_erase_range @ flash_erase_range   @ 19
        .word   flash_write_range@ flash_write_range        @ 20
        .word   bsc_ramload @ bsc_ramload           @ 21    
@--------------------------------------------------------------	    
	    .global	bsp
bsp:
	    nop
@-------------------------------------------------------------

PtTmp:	    .word	6
	    .word	7
#endif

	.ltorg
#if defined (AM29LV160D) || defined (HY29LV320B)
	.org 0x6000
#elif defined (SST39VF160)
	.org 0x1000
#else
	.org 0x4000
#endif