start.s

source code of armboot for s3c4510

/*
 *  armboot - Startup Code for ARM940T CPU-core
 *
 *  Copyright (c) 2001	Marius Gr?er <[e-mail]>
 *  Copyright (c) 2002	Alex Z?ke <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */



#include "config.h"
#include "version.h"
#if defined(CONFIG_S3C2500)
#include <s3c2500.h>
#endif
#if defined(CONFIG_S3C2510)
#include <s3c2510.h>
#endif

#define AMD_FLASH
#undef SAMSUNG_FLASH
#undef BDI2K

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:	b       reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

#ifdef CONFIG_UCBOOTSTRAP
		.space	28, 0			@
		.fill	1, 4, 0x485a4f00	@
		.word	reset

_undefined_instruction:	.word UndInstr
#else
_undefined_instruction:	.word undefined_instruction
#endif

_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

/*
 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
 */
_TEXT_BASE:
	.word	TEXT_BASE

.globl _armboot_start
_armboot_start:
	.word _start

/*
 * Note: armboot_end is defined by the (board-dependent) linker script
 */
.globl _armboot_end
_armboot_end:
	.word armboot_end

/*
 * _armboot_real_end is the first usable RAM address behind armboot
 * and the various stacks
 */
.globl _armboot_real_end
_armboot_real_end:
	.word 0x0badc0de

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif


/*
 * the actual reset code
 */

#ifndef BDI2K
reset:
	/* turn on the LED connected with GPIO0 */

	ldr		r0, =IOPMODE1
	ldr		r1, =0xf003ff00
	str		r1, [r0]

/* 
 * 1. SYSTEM CONFIGURATION & INTERRUPT DISABLE
*/
	ldr		r0, =CLKCON
	ldr		r1, =0x0			/* System Clock Dividing by 0 - non-divided clock is used */
	str		r1, [r0]

	ldr		r0, =SYSCFG			/* Clear all SYSCFG except REMAP, BIG(Read-only) */
	ldr		r1, [r0]
	and		r1, r1, #REMAP
	str		r1, [r0]

	ldr		r0, =HPRIR
	ldr		r1, =0x330			/* Ethernet controllers have highest arbitor priority */
	str		r1, [r0]

	ldr		r0, =PCLKDIS		/* All Clock Enable */
	ldr		r1, =ALLCLKENABLE
	str		r1, [r0]

	ldr		r0, =INTMASK 			
	ldr   	r1, =0xffffffff		/* All Interrupt Disable */
	str     r1, [r0]	
	ldr		r0, =EXTMASK 			
   	ldr   	r1, =0x8000007f		/* All Interrupt Disable */
	str     r1, [r0]    				

	ldr		r0, =INTMOD			/* All IRQ Mode */
	ldr		r1, =0
	str		r1, [r0]
	ldr		r0, =EXTMOD			/* All IRQ Mode */
	str		r1, [r0]
	
/*	bl		Clear_AllPendingReg  */ /* this is s3c2500 specific, and not required in armboot */

/*
 * 2. SDRAM  & OTHER MEMORY CONFIGURATION
 *	reference User's Manual, MEMORY CONTROLLER chapter, SDRAM initialization sequence
 */
	/*
	 * <1 > Wait 200us to allow SDRAM power and clocks to stabilize.
	 *		Wait Time  =(fMCLK/MHz)*200
	 */
	ldr		r0, =fMCLK*200
wait1:
	subs	r0, r0,#1
	bne	 	wait1
 
	/*
	 * <2> PALL COMMAND  SET:
	 *		Program the INIT[1:0] to 01(PALL).
	 */
	ldr     r0, =CMDREG
	ldr     r1, =SDR_PALL
	str     r1, [r0]

	/*
	 * <3> Every 15 CLOCK CYCLE REFRESH
	 *	Write 0xF into the refresh timer register.
	 */
	ldr		r0, =REFREG
	ldr		r1, =0xF     
	str		r1, [r0]     

	/* 
	 * <4> WAIT  FUNCTION:
	 *	Wait for a time period equivalent to 120 clock cycles (8 refresh cycles).
	 */
	ldr		r1, =0x78
wait2:
	subs	r1, r1,#1
	bne		wait2

	/*
	 * <5> NORMAL  REFRESH  CYCLE
	 *	Normal operational value into the refresh timer.
	 *	Common refresh time 15.6 usec     
	 *  SDRAM refresh time = fMCLK*15 + (6*fMCLK)/10     
	 */
	ldr		r1, =(fMCLK*15 + (6*fMCLK)/10)
	str		r1, [r0]

	/*
	 * <6> Program CFGREG to their normal operation values
	 */
	ldr		r0, =CFGREG
	ldr		r1, =rSDRAMCFGREG
	str		r1, [r0]

	/*
	 *<7> MRS  COMMAND  SET
	 *	Program the INIT[1:0] to 10. This automatically issues a MRS command to the SDRAM.
	 */
	ldr     r0, =CMDREG
	ldr     r1, =SDR_MRS
	str     r1, [r0]

	/*
	 * <8> SyncDRAM Configration Register Setting
	 *	Program the INIT[1:0] to 00. The controller enters the normal mode.    
	 */
	ldr     r0, =CMDREG
	ldr     r1, =SDR_NORMAL
	str     r1, [r0]

	/*
	 * <9> Program CMDREG and WBTOREG to their normal operation values
	 */
	ldr		r0, =CMDREG
	ldr		r1, =rSDRAMCMDREG
	str		r1, [r0]
	ldr		r0, =WBTOREG
	ldr		r1, =rSDRAMWBTO
	ldr		r1, [r0]

	/*
	 * Initialize Memory Controller for EEPROM/FLASH/SRAM
	 */
	adrl    r0, MEMCON_INITTBL
	ldmia   r0, {r1-r10}
	ldr		r0, =ASIC_BASE + 0x10000 			/* B0CON offset : 0x10000 */
	stmia   r0, {r1-r10}   		

/*
 * 4. GOTO SUPERVISOR MODE & IRQ/FIQ LOCKOUT
 */
	/* set the cpu to SVC32 mode*/
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0x13
	msr	cpsr,r0

/*
 * 5. PROTECTION OFF/ SETTING ENDIAN/ CLOCKING MODE
 */
	mrc 	p15, 0, r0, c1, c0, 0
	bic		r0, r0, #PROTECTION_ON		/* Protection Off */
	mcr 	p15, 0, r0, c1, c0, 0

	mcr 	p15, 0, r1, c1, c0, 0		/* Read CP15 Reg, C1(Control Register) */
	ldr	 	r0, =(nFASTBUS | ASYNC_CLK | 0x80)
	bic		r1, r1, r0					/* Clear Clocking Mode bit, Endian bit */
	
	ldr		r0, =CLKST
	ldr		r0, [r0]					/* CLCOK MODE from MCU input setting */
	and		r0, r0, #(nFASTBUS | ASYNC_CLK)
	orr		r1, r1, r0
	ldr		r0, =SYSCFG
	ldr		r0, [r0]					/* ENDIAN from MCU input setting */
	and     r0, r0, #BIG				
	mov		r0, r0, LSR #9
	orr		r1, r1, r0
	mcr 	p15, 0, r1, c1, c0, 0		/* Set CP15, C1 with CLOCK MODE, ENDIAN MODE */

relocate:
	 /* relocate armboot to RAM*/
 	adr	r0, _start					/* r0 <- current position of code */
 	ldr	r2, _armboot_start
 	ldr	r3, _armboot_end
 	sub	r2, r3, r2					/* r2 <- size of armboot */
 	ldr	r1, =0x40000000				/* r1 <- destination address */
 	add	r2, r0, r2					/* r2 <- source end address */

	 /* r0 = source address
	 * r1 = target address
	 * r2 = source end address*/
copy_loop:
 	ldmia	r0!, {r3-r10}
 	stmia	r1!, {r3-r10}
 	cmp	r0, r2
 	ble	copy_loop

	/* rom to ram address swapping */
REMAP_START_FOR_ROM:
    ldr 	r0, =SYSCFG
    ldr		r1, =REMAP
    
	ldr		r2, [r0]
	orr		r2, r2, r1
	str		r2, [r0]
	
	nop
	nop
	nop
	nop
	nop
#else 

reset:
	/* set system parameters */
	ldr     r0, =SYSCFG
	ldr     r1, =rSYSCFG
	str     r1, [r0]

	/* rom to ram address swapping */
	adr     r0, SDRAM_SYSINIT_BOOT
	ldmia   r0, {r1-r10} 
	ldr     r0, =SYS_INIT_BASE
	stmia   r0, {r1-r10}
		
	/* set the cpu to SVC32 mode*/
	mrs		r0,	cpsr
	bic		r0,	r0,	#0x1f
	orr		r0,	r0,	#0x13
	msr		cpsr, r0

	/* cache flushing */
	ldr	r0, =0x11000000
	mov	r1, #0
	mov	r2, #256

Cache_Flush_Loop:
	str     r1, [r0], #4
	subs    r2, r2, #1
	bne     Cache_Flush_Loop
#endif
		
	/* set up the stack */
	ldr	r0, _armboot_end
	add	r0, r0, #CONFIG_STACKSIZE
	sub	sp, r0, #12		/* leave 3 words for abort-stack */
	
	ldr	pc, _start_armboot
		
_start_armboot:	.word start_armboot

/*
 *************************************************************************
 *
 * Clear_AllPendingReg
 *
 * Clear All pending register
 *
 *************************************************************************
 */
Clear_AllPendingReg:

	/*
	 * nEXT0_INT (0), nEXT1_INT (1), nEXT2_INT (2), nEXT3_INT (3)
	 * nEXT4_INT (4), nEXT5_INT (5)
	 */
	 
	ldr		r0, =IOPEXTINTPND
	ldr		r1, =0x3f
	str		r1, [r0, #0]

	/*
	 * nIOM2_INT (6)
	 */
	
	ldr		r0, =IOM2STAT
	ldr		r1, =0x1ff5
	str		r1, [r0, #0]

	/*
	 * nIICC_INT (7)
	 */

	ldr		r0, =IICPND
	ldr		r1, =0x1
	str		r1, [r0, #0]

	/*
	 * nHUART0_TX_INT (8), nHUART0_RX_INT (9)
	 * nHUART1_TX_INT (10), nHUART1_RX_INT (11)
	 */

	ldr		r0, =HUSTAT0
	ldr		r1, =0x714ff
	str		r1, [r0, #0]
	ldr		r0, =HUSTAT1
	str		r1, [r0, #0]

	/*
	 * nCUART_TX_INT (12), nCUART_RX_INT (13)
	 */

	ldr		r0, =CUSTAT
	ldr		r1, =0x6003f
	str		r1, [r0, #0]
	
	/*
	 * nUSB_INT (14)
	 */

	ldr		r0, =USBINTR
	ldr		r1, =0xf1f
	str		r1, [r0, #0]

	/*
	 * nHDLC_TX0_INT (15), nHDLC_RX0_INT (16), nHDLC_TX1_INT (17), nHDLC_RX1_INT (18)
	 * nHDLC_TX2_INT (19), nHDLC_RX2_INT (20)
	 */

	ldr		r0, =HSTAT0
	ldr		r1, =0xedcffff0
	str		r1, [r0, #0]
	ldr		r0, =HSTAT1
	str		r1, [r0, #0]
	ldr		r0, =HSTAT2
	str		r1, [r0, #0]

	/*
	 * nMACA_TX_INT (21), nMACA_RX_INT (22), nMACB_TX_INT (23), nMACB_RX_INT (24)
	 */

	ldr		r0, =BMTXSTATA			/* For S3C2500 MAC, writing '0' will erase status register */
	ldr		r1, =0x0
	str		r1, [r0, #0]
	ldr		r0, =BMTXSTATB
	str		r1, [r0, #0]
	
	ldr		r0, =BMRXSTATA
	ldr		r1, =0x0
	str		r1, [r0, #0]
	ldr		r0, =BMRXSTATB
	str		r1, [r0, #0]
	
	/*
	 * nDES_INT (25)				; DES Interrupt disable
	 */

	ldr		r0, =DESINT
	ldr		r1, =0x0
	str		r1, [r0, #0]

	/* 
	 * nGDMA0_INT (26), nGDMA1_INT (27), nGDMA2_INT (28), nGDMA3_INT (29),
	 * nGDMA4_INT (30), nGDMA5_INT (31)
	 */

	ldr		r0, =DIPR0
	ldr		r1, =0x1
	str		r1, [r0, #0]
	ldr		r0, =DIPR1
	str		r1, [r0, #0]
	ldr		r0, =DIPR2
	str		r1, [r0, #0]
	ldr		r0, =DIPR3
	str		r1, [r0, #0]
	ldr		r0, =DIPR4
	str		r1, [r0, #0]
	ldr		r0, =DIPR5
	str		r1, [r0, #0]
	
	/*
	 * nTIMER0_INT (32), nTIMER1_INT (33), nTIMER2_INT (34), nTIMER3_INT (35),