s3c2500.h

source code of armboot for s3c4510

/*************************************************************************
* SYSTEM MEMORY CONTROL REGISTER EQU TABLES 
*/
/* ----------------------------------------------------------------------------- */
/* EXTERNAL I/O BANK CONTROL SPECIAL REGISTER EQU TABLES
* ----------------------------------------------------------------------------- */

/*   BANK CONTROL REGISTER      */

#define DW_SFT		30				/* Physical memory data bus width */
									/*	0=Reserved,1=8it, 2=16bit, 3=32bit */
#define PMC_SFT		28				/* Page mode configuration */
									/*	0=Normal ROM or External I/O, 1=4word, 2=8word, 3=16word */
#define BS_SFT		24				/* Bank Sizeize0 */
									/*	0=Disable, 1=1M, 2=2M, 3=4M, 4=8M, 5=16M */
#define IS_SFT		23				/* nWBE or nBE/DQM selection (nWBE is only for writing operation, nBE/DQM is for reading/writing)*/
									/*	0=nWBE function (8-bit), 1=nBE function (16-bit) */
#define TACC_SFT	16				/* Access cycles (nOE low time) */
									/*	0x3 = 3cycles, 0x4 = 4cycles, 0x5 = 5cycles, 0x6 = 6cycles, 0x7 = 7cycles */
									/*	0x8 = 8cycles, 0x9 = 9cycles, 0xA =10cycles, 0xB =11cycles, 0xC =12cycles */
									/*	0xD =13cycles, 0xE =14cycles, 0xF =15cycles, 0x10=16cycles, 0x11=17cycles */
									/*	0x12=18cycles, 0x13=19cycles, 0x14=20cycles, 0x15=21cycles, 0x16=22cycles */
									/*	0x17=23cycles, 0x18=24cycles, 0x19=25cycles, 0x1A=26cycles, 0x1B=27cycles */
									/*	0x1C=28cycles, 0x1D=29cycles, 0x1E=30cycles, 0x1F=31cycles */
#define TPA_SFT		12				/* Page address access cycle */
#define TACS_SFT	8				/* Address setup time */
#define TCOS_SFT	4				/* Chip selection setup time on nOE */
#define TCOH_SFT	0				/* Chip selection hold time on nOE */
									/*	0x3 = 3cycles, 0x4 = 4cycles ~ 0xF =15cycles */

#define rB0CON_0	0x14<<TACC_SFT+ 0xe<<TPA_SFT+ 0x4<<TACS_SFT+ 0x8<<TCOS_SFT+ 0x8<<TCOH_SFT
#define rB0CON   	1<<DW_SFT + 0<<PMC_SFT + 5<<BS_SFT + 0<<IS_SFT + rB0CON_0

#define rB1CON_0	0x14<<TACC_SFT + 0xe<<TPA_SFT + 0x4<<TACS_SFT + 0x8<<TCOS_SFT + 0x8<<TCOH_SFT
#define rB1CON   	2<<DW_SFT + 0<<PMC_SFT + 5<<BS_SFT + 0<<IS_SFT + rB1CON_0

#define rB2CON_0	((0x14<<TACC_SFT)+(0xe<<TPA_SFT)+(0x4<<TACS_SFT)+(0x8<<TCOS_SFT)+(0x8<<TCOH_SFT))
#define rB2CON   	((3<<DW_SFT)+(0<<PMC_SFT)+(5<<BS_SFT)+(1<<IS_SFT)+rB2CON_0)

#define rB3CON_0	((0xa<<TACC_SFT)+(0xe<<TPA_SFT)+(0x0<<TACS_SFT)+(0x0<<TCOS_SFT)+(0x1<<TCOH_SFT))
#define rB3CON   	((3<<DW_SFT)+(0<<PMC_SFT)+(5<<BS_SFT)+(1<<IS_SFT)+rB3CON_0)

#define rB4CON_0	((0xa<<TACC_SFT)+(0xe<<TPA_SFT)+(0x0<<TACS_SFT)|(0x0<<TCOS_SFT)+(0x1<<TCOH_SFT))
#define rB4CON   	((3<<DW_SFT)+(0<<PMC_SFT)+(5<<BS_SFT)+(1<<IS_SFT)+rB4CON_0)

#define rB5CON_0	((0xa<<TACC_SFT)+(0xe<<TPA_SFT)+(0x0<<TACS_SFT)+(0x0<<TCOS_SFT)+(0x1<<TCOH_SFT))
#define rB5CON   	((3<<DW_SFT)+(0<<PMC_SFT)+(5<<BS_SFT)+(1<<IS_SFT)+rB5CON_0)

#define rB6CON_0	((0xa<<TACC_SFT)+(0xe<<TPA_SFT)+(0x0<<TACS_SFT)+(0x1<<TCOS_SFT)+(0x1<<TCOH_SFT))
#define rB6CON   	((3<<DW_SFT)+(0<<PMC_SFT)+(5<<BS_SFT)+(1<<IS_SFT)+rB6CON_0)

#define rB7CON_0	((0xa<<TACC_SFT)+(0xe<<TPA_SFT)+(0x0<<TACS_SFT)+(0x1<<TCOS_SFT)+(0x1<<TCOH_SFT))
#define rB7CON   	((3<<DW_SFT)+(0<<PMC_SFT)+(5<<BS_SFT)+(1<<IS_SFT)+rB7CON_0)


/*	MUXBCON: Muxed Bus Control Register  */

#define MBE7		0x0<<31		/* 0x0=disable, 0x1=enable */
#define MBE6		0x0<<30	
#define MBE5		0x0<<29	
#define MBE4		0x0<<28	
#define MBE3		0x0<<27	
#define MBE2		0x0<<26	
#define MBE1		0x0<<25	
#define MBE0		0x0<<24	

#define TMA7		0x3<<21		/* 0x0=2cycles, 0x1=3cycle, 0x2=4cycle, 0x3=5cycle */
#define TMA6		0x3<<18   	/* 0x4=6cycles, 0x5=7cycle, 0x6=8cycle, 0x9=5cycle */
#define TMA5		0x3<<15   	
#define TMA4		0x3<<12	
#define TMA3		0x3<<9   	
#define TMA2		0x3<<6   	
#define TMA1		0x3<<3   	
#define TMA0		0x3<<0	

#define ALLMUXEN	(0xff<<24)
#define AULLMUXDIS	(0x0<<0)

#define rMUXBCON   	MBE7+MBE6+MBE5+MBE4+MBE3+MBE2+MBE1+MBE0+TMA7+TMA6+TMA5+TMA4+TMA3+TMA2+TMA1+TMA0


/*	WAITCON: Wait Control Register       */

#define COHDIS7		0x1<<23		/* This forces TCOH to '0' for read to read, write to write, */
	                            /* and write to read access in bank 7 */
#define COHDIS6		0x1<<22     /* 0: disable  1: enable */
#define COHDIS5		0x1<<21
#define COHDIS4		0x1<<20
#define COHDIS3		0x1<<19
#define COHDIS2		0x1<<18
#define COHDIS1		0x1<<17
#define COHDIS0		0x1<<16

#define EWAITEN7	0x0<<15		/* External wait enable for bank(n) 0 : disable,  1 : enable */
#define EWAITEN6	0x0<<14
#define EWAITEN5	0x0<<13
#define EWAITEN4	0x0<<12
#define EWAITEN3	0x0<<11
#define EWAITEN2	0x0<<10
#define EWAITEN1	0x0<<9	
#define EWAITEN0	0x0<<8
	
#define NREADY7		0x0<<7		/* nWait / nReady select for bank(n) 0 = nWait,   1 = nReady */
#define NREADY6		0x0<<6	
#define NREADY5		0x0<<5
#define NREADY4		0x0<<4
#define NREADY3		0x0<<3
#define NREADY2		0x0<<2
#define NREADY1		0x0<<1
#define NREADY0		0x0<<0

#define rCOHDIS     COHDIS7+COHDIS6+COHDIS5+COHDIS4+COHDIS3+COHDIS2+COHDIS1+COHDIS0
#define rEWAITEN	EWAITEN7+EWAITEN6+EWAITEN5+EWAITEN4+EWAITEN3+EWAITEN2+EWAITEN1+EWAITEN0
#define rNREADY		NREADY7+NREADY6+NREADY5+NREADY4+NREADY3+NREADY2+NREADY1+NREADY0

#define rWAITCON	rCOHDIS+rEWAITEN+rNREADY
									/* Extern wait enable for bank (n)= disable */
									/* Bank (n) Wait single  : nWait */
									
/* ----------------------------------------------------------------------------- */
/* SDRAM CONTROL SPECIAL REGISTER TABLS										 */
/* ----------------------------------------------------------------------------- */

/*	CFGREG: SDRAM CONFIGURATION REGISTER 0	*/

#define SDR_XW		(0x0<<0)	/* External data bus Width, 0x0=32bit, 0x1=16it */
#define SDR_AP		(0x0<<1)	/* Auto Pre-charge control for SDRAM accesses, 0x0=Auto Pre-charge, 0x1=No Auto Pre-charge */
#define SDR_CL		(0x3<<2)	/* CAS Latency, 0x0=Reserved 0x1=1cycle, 0x2=2cycles, 0x3=3cycles */
#define SDR_D1		(0x2<<4)	/* SDRAM divice Density of bank 1, 0x0=16Mbit,  0x1=64Mbit, 0x2=128Mbit, 0x3=256Mbit */
#define SDR_D0		(0x2<<6)	/* SDRAM divice Density of bank 1, 0x0=16Mbit,  0x1=64Mbit, 0x2=128Mbit, 0x3=256Mbit */
#define SDR_RP		(0x2<<8)	/* Row Pre-charge time, 0x0=1cycle, 0x1=2cycle, 0x2=3cycles, 0x3=4cycles */
#define SDR_RCD		(0x2<<10)	/* RAS to CAS delay, 0x0=1cycle   0x1=2cycle, 0x2=3cycles, 0x3=4cycles */	
#define SDR_RC		(0x8<<12)	/* Row Cycle, 0x0=1cycle, 0x1=2cycle ~ 0xf=16cycles */
#define SDR_RAS		(0x5<<16)	/* Row Active time, 0x0=1cycle, 0x1=2cycle ~  0xf=16cycles */

#define rSDRAMCFGREG	SDR_XW+SDR_AP+SDR_CL+SDR_D1+SDR_D0+SDR_RP+SDR_RCD+SDR_RC+SDR_RAS

/*	CMDREG: SDRAM CONFIGURATION REGISTER 1  */

#define SDR_INITS		(0x0<<0)	/* Control bits for SDRAM Device initialization */
									/*	0x0=Normal operation 0x3=Reserved */										
									/*	0x1=Auto issue a PALL to the SDRAM */
									/*	0x2=Auto issue a MRS  tot the SDRAM */
#define SDR_NORMAL		(0x0<<0)										
#define SDR_PALL		(0x1<<0)
#define SDR_MRS 		(0x2<<0)		
#define SDR_WBUF		(0x0<<2)	/* Write Buffer Enable */
									/*	0x0=Merging Write buffer disable */
									/*	0x1=Merging Write buffer enable */
#define SDR_BUSY		(0x1<<3)	/* SDRAM controller status bit (READ ONLY) */
									/*	0x0: IDLE, 0x1: BUSY */

/*	CMDREG: SDRAM CONFIGURATION REGISTER 1  */

#define rSDRAMCMDREG	SDR_INITS+SDR_WBUF
										/* Refresh	= 	(15.6*(fMCLK/Mhz)) */
										/* SDRAMCONFIG1 = (fMCLK/Mhz)*15 + (6*(fMCLK/Mhz))/10 */
										/* Clock >= 64/(15.6*Mhz) = 4.3Mh */
										/* Common refresh time period of 15.6us , SYSTEM CLK 66Mhz */
										/*	15.6Mhz X 66Mhz = 1029  refresh time */
#define rSDRAMWBTO		0x0

/* ----------------------------------------------------------------------------- */
/* S3C2500X Interrupt Number (Index value of interrupt sources)					*/
/* ----------------------------------------------------------------------------- */

#define INT_NUM_LEVELS	39
#define INT_ALL_MASK	0xffffffff
#define EXT_ALL_MASK	0x8000007f

#define	NR_EXT_IRQS	7		/* External interrupt sources number */

/* External Interrupt */
#define INT_LVL_EXT0			0	/* External Interrupt 0 */
#define INT_LVL_EXT1			1	/* External Interrupt 1 */
#define INT_LVL_EXT2			2	/* External Interrupt 2 */
#define INT_LVL_EXT3			3	/* External Interrupt 3 */
#define INT_LVL_EXT4			4	/* External Interrupt 4 */
#define INT_LVL_EXT5			5	/* External Interrupt 5 */
#define INT_LVL_IOM2			6	/* IOM2 Interrupt */

#define NR_INT_IRQS	32		/* Internal interrupt sources number */

/* Internal Interrupt */
#define INT_LVL_IICC			7	/* IICC Interrupt */
#define INT_LVL_HUART0_TX		8	/* HUART0 TX Interrupt */
#define INT_LVL_HUART0_RX		9	/* HUART0 RX Interrupt */
#define INT_LVL_HUART1_TX		10	/* HUART1 TX Interrupt */
#define INT_LVL_HUART1_RX		11	/* HUART1 RX Interrupt */
#define INT_LVL_CUART_TX		12	/* CUART TX Interrupt */
#define INT_LVL_CUART_RX		13	/* CUART RX Interrupt */
#define INT_LVL_USB				14	/* USB Interrupt */
#define INT_LVL_HDLC_TX0		15	/* HDLC Tx0 Interrupt */
#define INT_LVL_HDLC_RX0		16	/* HDLC Rx0 Interrupt */
#define INT_LVL_HDLC_TX1		17	/* HDLC Tx1 Interrupt */
#define INT_LVL_HDLC_RX1		18	/* HDLC Rx1 Interrupt */
#define INT_LVL_HDLC_TX2		19	/* HDLC Tx2 Interrupt */
#define INT_LVL_HDLC_RX2		20	/* HDLC Rx2 Interrupt */
#define INT_LVL_ETHTxA			21	/* Ethernet TX0 Interrupt */
#define INT_LVL_ETHRxA			22	/* Ethernet RX0 Interrupt */
#define INT_LVL_ETHTxB			23	/* Ethernet Tx1 Interrupt */
#define INT_LVL_ETHRxB			24	/* Ethernet Rx1 Interrupt */
#define INT_LVL_DES				25	/* DES Interrupt */
#define INT_LVL_GDMA0			26	/* GDMA Channel 0 Interrupt */
#define INT_LVL_GDMA1			27	/* GDMA Channel 1 Interrupt */
#define INT_LVL_GDMA2			28	/* GDMA Channel 2 Interrupt */
#define INT_LVL_GDMA3			29	/* GDMA Channel 3 Interrupt */
#define INT_LVL_GDMA4			30	/* GDMA Channel 4 Interrupt */
#define INT_LVL_GDMA5			31	/* GDMA Channel 5 Interrupt */
#define INT_LVL_TIMER0			32	/* 32-bit Timer 0 Interrupt */
#define INT_LVL_TIMER1			33	/* 32-bit Timer 1 Interrupt */
#define INT_LVL_TIMER2			34	/* 32-bit Timer 2 Interrupt */
#define INT_LVL_TIMER3			35	/* 32-bit Timer 3 Interrupt */
#define INT_LVL_TIMER4			36	/* 32-bit Timer 4 Interrupt */
#define INT_LVL_TIMER5			37	/* 32-bit Timer 5 Interrupt */
#define INT_LVL_WATCHDOG		38	/* Watchdog Timer Interrupt */

/* 20020612 by drsohn */
#define VPint	*(volatile unsigned int *)
#define UARTSTAT0           (VPint(ASIC_BASE+0x60004))
#define UARTTXH0            (VPint(ASIC_BASE+0x6000c))
#define UARTRXB0            (VPint(ASIC_BASE+0x60010))
/* drsohn end */

//-----------------------------------------------------------------------------
// Declare function protype
//-----------------------------------------------------------------------------
/*
extern void reset_cpu(ulong addr);
extern void intDisable(int vect);
*/
#define CONFIG_UCBOOTSTRAP			/* Use uCboot emulation */

#endif