s3c2500.h

source code of armboot for s3c4510

#define HBRGTC1			(ASIC_BASE+0x10001c + 1*0x10000)	/* HDLC BRG time constant register */
#define HPRMB1	 		(ASIC_BASE+0x100020 + 1*0x10000)	/* HDLC preamble register */
#define HSAR01 			(ASIC_BASE+0x100024 + 1*0x10000)	/* HDLC station address 0 */
#define HSAR11	 		(ASIC_BASE+0x100028 + 1*0x10000)	/* HDLC station address 1 */
#define HSAR21	 		(ASIC_BASE+0x10002c + 1*0x10000)	/* HDLC station address 2 */
#define HSAR31	 		(ASIC_BASE+0x100030 + 1*0x10000)	/* HDLC station address 3 */
#define HMASK1 			(ASIC_BASE+0x100034 + 1*0x10000)	/* HDLC mask register */
#define HDMATXPTR1		(ASIC_BASE+0x100038 + 1*0x10000)	/* DMA Tx buffer descriptor pointer */
#define HDMARXPTR1		(ASIC_BASE+0x10003c + 1*0x10000)	/* DMA Rx buffer descriptor pointer */
#define HMFLR1 			(ASIC_BASE+0x100040 + 1*0x10000)	/* Maximum frame length register */
#define HRBSR1 			(ASIC_BASE+0x100044 + 1*0x10000)	/* Receive buffer size register */
#define HSYNC1			(ASIC_BASE+0x100048 + 1*0x10000)	/* HDLC Sync Register */
#define TCON1			(ASIC_BASE+0x10004c + 1*0x10000)	/* Transparent Control regiseter */
#define HTXBDCNT1		(ASIC_BASE+0x1000c0 + 1*0x10000)	/* Tx buffer descriptor count register */
#define HRXBDCNT1		(ASIC_BASE+0x1000c4 + 1*0x10000)	/* Rx buffer descriptor count register */
#define HTXMAXBDCNT1	(ASIC_BASE+0x1000c8 + 1*0x10000)	/* Tx buffer descriptor count mask register */
#define HRXMAXBDCNT1	(ASIC_BASE+0x1000cc + 1*0x10000)	/* Rx buffer descriptor count mask register */

#define HMODE2	 		(ASIC_BASE+0x100000 + 2*0x10000)	/* HDLC mode register */	             
#define HCON2 			(ASIC_BASE+0x100004 + 2*0x10000)	/* HDLC control register */          
#define HSTAT2  		(ASIC_BASE+0x100008 + 2*0x10000)	/* HDLC status register */
#define HINTEN2 		(ASIC_BASE+0x10000c + 2*0x10000)	/* HDLC interrupt enable register */
#define HTXFIFOC2 		(ASIC_BASE+0x100010 + 2*0x10000)	/* HTxFIFO frame continue register */
#define HTXFIFOT2 		(ASIC_BASE+0x100014 + 2*0x10000)	/* HTxFIFO frame terminate register */
#define HRXFIFO2 		(ASIC_BASE+0x100018 + 2*0x10000)	/* HRxFIFO entry register */
#define HBRGTC2			(ASIC_BASE+0x10001c + 2*0x10000)	/* HDLC BRG time constant register */
#define HPRMB2		 	(ASIC_BASE+0x100020 + 2*0x10000)	/* HDLC preamble register */
#define HSAR02 			(ASIC_BASE+0x100024 + 2*0x10000)	/* HDLC station address 0 */
#define HSAR12	 		(ASIC_BASE+0x100028 + 2*0x10000)	/* HDLC station address 1 */
#define HSAR22	 		(ASIC_BASE+0x10002c + 2*0x10000)	/* HDLC station address 2 */
#define HSAR32	 		(ASIC_BASE+0x100030 + 2*0x10000)	/* HDLC station address 3 */
#define HMASK2 			(ASIC_BASE+0x100034 + 2*0x10000)	/* HDLC mask register */
#define HDMATXPTR2		(ASIC_BASE+0x100038 + 2*0x10000)	/* DMA Tx buffer descriptor pointer */
#define HDMARXPTR2		(ASIC_BASE+0x10003c + 2*0x10000)	/* DMA Rx buffer descriptor pointer */
#define HMFLR2 			(ASIC_BASE+0x100040 + 2*0x10000)	/* Maximum frame length register */
#define HRBSR2 			(ASIC_BASE+0x100044 + 2*0x10000)	/* Receive buffer size register */
#define HSYNC2			(ASIC_BASE+0x100048 + 2*0x10000)	/* HDLC Sync Register */
#define TCON2			(ASIC_BASE+0x10004c + 2*0x10000)	/* Transparent Control regiseter */
#define HTXBDCNT2		(ASIC_BASE+0x1000c0 + 2*0x10000)	/* Tx buffer descriptor count register */
#define HRXBDCNT2		(ASIC_BASE+0x1000c4 + 2*0x10000)	/* Rx buffer descriptor count register */
#define HTXMAXBDCNT2	(ASIC_BASE+0x1000c8 + 2*0x10000)	/* Tx buffer descriptor count mask register */
#define HRXMAXBDCNT2	(ASIC_BASE+0x1000cc + 2*0x10000)	/* Rx buffer descriptor count mask register */


/* ----------------------------------------------------------------------------- */
/* IOM2  Control Registers            ((0xF0130000 ~ 0xF013FFFF))	            */
/* ----------------------------------------------------------------------------- */

#define IOM2CON			(ASIC_BASE+0x130000)		/* IOM2 Control Register */
#define IOM2STAT		(ASIC_BASE+0x130004)		/* Status Register */
#define IOM2INTEN		(ASIC_BASE+0x130008)		/* Interrupt Enable Register */
#define IOM2TBA			(ASIC_BASE+0x13000C)		/* TIC Bus Address */
#define IOM2ICTD		(ASIC_BASE+0x130010)		/* IC ch Tx Buffer */
#define IOM2ICRD		(ASIC_BASE+0x130014)		/* IC ch Rx Buffer */
#define IOM2CITD0		(ASIC_BASE+0x130018)		/* C/I0 ch Tx Buffer */
#define IOM2CIRD0		(ASIC_BASE+0x13001C)		/* C/I0 ch Rx Buffer */
#define IOM2CITD1		(ASIC_BASE+0x130020)		/* C/I1 ch Tx Buffer */
#define IOM2CIRD1		(ASIC_BASE+0x130024)		/* C/I1 ch Rx Buffer */
#define IOM2MTD			(ASIC_BASE+0x130028)		/* Monitor ch Tx Buffer */
#define IOM2MRD			(ASIC_BASE+0x13002C)		/* Monitor ch Rx Buffer */
#define TSAACON			(ASIC_BASE+0x130030)		/* TSA A Configuration Register */
#define TSABCON			(ASIC_BASE+0x130034)		/* TSA B Configuration Register */
#define TSACCON			(ASIC_BASE+0x130038)		/* TSA C Configuration Register */
#define IOM2STRB		(ASIC_BASE+0x13003C)		/* IOM2 Strobe Set Register */

/* Used in DiagCode */
#define IOM2CITD(c)		(ASIC_BASE+0x130018 + c*0x8)	/* C/I ch Tx Buffer */
#define IOM2CIRD(c)		(ASIC_BASE+0x13001C + c*0x8)	/* C/I ch Rx Buffer */

#define TSAACFG			(ASIC_BASE+0x130030)		/* TSA A Configuration Register */
#define TSABCFG			(ASIC_BASE+0x130034)		/* TSA B Configuration Register */
#define TSACCFG			(ASIC_BASE+0x130038)		/* TSA C Configuration Register */

/* ----------------------------------------------------------------------------- */
/* INTERRUPT  Control Registers            (0xF0140000 ~ 0xF014FFFF)		    */
/* ----------------------------------------------------------------------------- */

#define INTMOD			(ASIC_BASE+0x140000)   	/* Internal interrupt mode register */
#define EXTMOD			(ASIC_BASE+0x140004)  	/* External interrupt mode register */
#define INTMASK			(ASIC_BASE+0x140008)  	/* Internal Interrupt mask register */
#define EXTMASK			(ASIC_BASE+0x14000C)  	/* External Interrupt mask register */
#define IPRIORHI		(ASIC_BASE+0x140010)  	/* High bits,5~0 bit, Interrupt by priority register */
#define IPRIORLO		(ASIC_BASE+0x140014)  	/* Low bits, 31~0 bit, Interrupt by priority register */
#define INTOFFSET_FIQ		(ASIC_BASE+0x140018)  	/* FIQ interrupt offset register */
#define INTOFFSET_IRQ		(ASIC_BASE+0x14001C)  	/* IRQ interrupt offset register */
#define INTPRIOR0		(ASIC_BASE+0x140020)  	/* Interrupt priority register 0 */
#define INTPRIOR1		(ASIC_BASE+0x140024)  	/* Interrupt priority register 1 */
#define INTPRIOR2		(ASIC_BASE+0x140028)  	/* Interrupt priority register 2 */
#define INTPRIOR3		(ASIC_BASE+0x14002C)  	/* Interrupt priority register 3 */
#define INTPRIOR4		(ASIC_BASE+0x140030)  	/* Interrupt priority register 4 */
#define INTPRIOR5		(ASIC_BASE+0x140034)  	/* Interrupt priority register 5 */
#define INTPRIOR6		(ASIC_BASE+0x140038)  	/* Interrupt priority register 6 */
#define INTPRIOR7		(ASIC_BASE+0x14003C)  	/* Interrupt priority register 7 */
#define INTPRIOR8		(ASIC_BASE+0x140040)  	/* Interrupt priority register 8 */
#define INTPRIOR9		(ASIC_BASE+0x140044)  	/* Interrupt priority register 9 */
#define INTTST			(ASIC_BASE+0x140048)  	/* Interrupt test register */
#define EXTTST			(ASIC_BASE+0x14004C)  	/* Interrupt test register */

/* ----------------------------------------------------------------------------- */
/* UART STATUS BITS																*/
/* ----------------------------------------------------------------------------- */
/* CUCON: Console UART control defines */

/* bit 1:0 */
#define	TxModeCpu		0x01	// UART Transmit mode interrupt request 
#define	TxModeGDMA		0x02    // UART Transmit mode GDMA (Only for High Speed UART)
/* bit 3:2 */
#define	RxModeCpu		0x04    // UART Receive mode  interrupt request         
#define	RxModeGDMA		0x08    // UART Receive mode  GDMA (Use High Speed UART)
/* bit 4 */
#define	Send_Break		0x010	// Send Break            
#define	No_Break		0x000
/* bit 5 */
#define	Serial_Clock	0x000	// Serial Clock Internal
#define	Serial_ExtClock	0x020	// Serial Clock External
/* bit 6 */
#define	ABRD			0x040	// Auto Baud Rate Detect(Use High Speed UART)	
/* bit 7 */
#define	Loop_Back		0x080	// Loop-back mode 
/* bit 10:8 */
#define	Parity_Mask			0x700   // Parity mode           
#define	Parity_None			0x000
#define	Parity_Odd			0x400          
#define	Parity_Even			0x500
#define	Parity_1			0x600
#define	Parity_0			0x700
/* bit 11 */
#define	Stop_Bits_Mask		0x00000800	// Number of Stop bits   
#define	One_Stop_Bit		0x00000000
#define	Two_Stop_Bits		0x00000800
/* bit 13:12 */
#define	Data_Length_5		0x0000		// Word Length 
#define	Data_Length_6		0x1000
#define	Data_Length_7		0x2000
#define	Data_Length_8		0x3000
#define	Data_Length_Mask	0x3000
/* bit 14 */
#define	Infra_Red_Mode		0x4000		// Infra-red mode
/* bit 29 */
#define	Flow_Software		(0x1<<29)	// S/W Flow control
/* bit 30 */
#define	Uart_Echo			(0x1<<30)	// Echo RX data to TX port directly

/* CUSTAT: Console UART status register */

/* Rx error */
#define RX_ERROR			(0x1c)		// OVERRUN/ PARITY/ FRAMING 
/* bit 0 */
#define Uart_Rx_Data_Ready	(0x1<<0)	// Receive Data Valid (RDV)
/* bit 1 */
#define Uart_Break_Detected	(0x1<<1)	// Break Signal Detected (BSD)
/* bit 2 */
#define Uart_Frame_Err		(0x1<<2)	// Frame Error (FER)
/* bit 3 */
#define Uart_Parity_Err		(0x1<<3)	// Parity Error (PER)
/* bit 4 */
#define Uart_Overrun_Err	(0x1<<4)	// Overrun Error(OER)
/* bit 5 */
#define Uart_Control_Detect	(0x1<<5)	// Control Caracter Detect (CCD)
/* bit 11 */
#define Uart_Rx_Idle		(0x1<<11)	// Receiver in idle (RXIDLE)
/* bit 17 */
#define Uart_Tx_Complete	(0x1<<17)	// Transmitter Idle (TI)
/* bit 18 */
#define Uart_Tx_Data_Ready	(0x1<<18)	// Transmit Holding Register Empty (THE)

/* CUINT: Console UART interrupt register */

#define	ENABLE_TX_RX		(Uart_Rx_Data_Ready | Uart_Tx_Data_Ready)
/* bit 0 */
#define	UART_RDVIE			Uart_Rx_Data_Ready	// Receive Data Valid interrupt enable
/* bit 1 */
#define	UART_BSDIE			Uart_Break_Detected	// Break Signal Detected interrupt enable
/* bit 2 */
#define	UART_FERIE			Uart_Frame_Err		// Frame Error interrupt enable
/* bit 3 */
#define	UART_PERIE			Uart_Parity_Err		// Parity Error interrupt enable
/* bit 4 */
#define	UART_OERIE			Uart_Overrun_Err	// Overrun Error interrupt enable
/* bit 5 */
#define	UART_CCDIE			Uart_Control_Detect	// Control Character Detect interrupt enable
/* bit 17 */
#define	UART_TIIE			Uart_Tx_Complete	// Transmitter idle interrupt enable
/* bit 18 */
#define	UART_THEIE			Uart_Tx_Data_Ready	// Transmit Holding Register Empty interrupt enable

#ifndef REG_READ
#define REG_READ(reg, result) \
	((result) = *(volatile ulong *)(reg))
#endif /*READ REG*/

#ifndef REG_WRITE
#define REG_WRITE(reg, data) \
	(*((volatile ulong *)(reg)) = (data))
#endif /*WRITE REG*/

/*************************************************************************
*
* DRAM Memory Bank 0 area MAP for Exception vector table 
* and Stack, User code area. 
*
*/

#define DRAM_BASE  			0x0				/* Final start address of DRAM */
#define DRAM_LIMIT 			0x2000000		/* 32MByte */
#define RESET_DRAM_START	0x40000000		/* Start of DRAM on power-up */
#define RESET_ROM_START		0x0				/* Start od ROM on power-up */

/****************************************************************************
*
* Format of the Program Status Register 
*/

#define FBit 	 	0x40
#define IBit  	 	0x80
#define LOCKOUT  	0xC0 	/* Interrupt lockout value */
#define LOCK_MSK 	0xC0 	/* Interrupt lockout mask value */
#define MOD_MASK 	0x1F 	/* Processor Mode Mask */
#define UDF_MODE 	0x1B 	/* Undefine Mode(UDF) */
#define ABT_MODE 	0x17 	/* Abort Mode(ABT) */
#define SUP_MODE 	0x13 	/* Supervisor Mode (SVC) */
#define IRQ_MODE 	0x12 	/* Interrupt Mode (IRQ) */
#define FIQ_MODE 	0x11 	/* Fast Interrupt Mode (FIQ) */
#define USR_MODE 	0x10 	/* User Mode(USR) */

/* ----------------------------------------------------------------------------- */
/*  Define ARM CPSR and MMU Value										        */
/* ----------------------------------------------------------------------------- */
/* REGISTER 1 */
#define PROTECTION_ON	(0x1<<0)
#define DC_ON			(0x1<<2)
#define BIG_END			(0x1<<7)
#define IC_ON			(0x1<<12)
#define nFASTBUS		(0x1<<30)
#define ASYNC_CLK		(0x1<<31)

/* REGISTER 6 */
#define REGION_ENABLE	(0x1<<0)