s3c2500.h

source code of armboot for s3c4510

#define TIMER_TDATA_4			(ASIC_BASE+0x40030)	/* Timer4 data register */
#define TIMER_TCNT_4			(ASIC_BASE+0x40034)	/* Timer4 counter register */
#define TIMER_TDATA_5			(ASIC_BASE+0x40038)	/* Timer5 data register */
#define TIMER_TCNT_5			(ASIC_BASE+0x4003c)	/* Timer5 counter register */

/* Used in DiagCode */
#define TIMER_TDATA(ch)		(ASIC_BASE+0x40010 + ch*0x8) /* Timer  data register */
#define TIMER_TCNT(ch)		(ASIC_BASE+0x40014 + ch*0x8) /* Timer  counter register */
#define WATCHDOG		WDT

/* ----------------------------------------------------------------------------- */
/* GDMA Ch 0/1/2/3/4/5   Control Registers        (0xF0050000 ~ 0xF005FFFF)		*/
/* ----------------------------------------------------------------------------- */

#define DPRIC			(ASIC_BASE+0x51000)			/* GDMA priority configuration register */
#define DPRIF			(ASIC_BASE+0x52000)			/* GDMA programmable priority register for fixed */
#define DPRIR			(ASIC_BASE+0x53000)			/* GDMA programmable priority register for round-robin */
#define DCON0			(ASIC_BASE+0x50000 + 0*0x20)	/* GDMA ch control register */
#define DSAR0			(ASIC_BASE+0x50004 + 0*0x20)	/* GDMA ch source address register */
#define DDAR0			(ASIC_BASE+0x50008 + 0*0x20)	/* GDMA ch destination address register */
#define DTCR0			(ASIC_BASE+0x5000C + 0*0x20)	/* GDMA ch transfer count register */
#define DRER0			(ASIC_BASE+0x50010 + 0*0x20)	/* GDMA ch run enable register */
#define DIPR0			(ASIC_BASE+0x50014 + 0*0x20)	/* GDMA ch interrupt pending register */
#define DCON1			(ASIC_BASE+0x50000 + 1*0x20)	/* GDMA ch control register */
#define DSAR1			(ASIC_BASE+0x50004 + 1*0x20)	/* GDMA ch source address register */
#define DDAR1			(ASIC_BASE+0x50008 + 1*0x20)	/* GDMA ch destination address register */
#define DTCR1			(ASIC_BASE+0x5000C + 1*0x20)	/* GDMA ch transfer count register */
#define DRER1			(ASIC_BASE+0x50010 + 1*0x20)	/* GDMA ch run enable register */
#define DIPR1			(ASIC_BASE+0x50014 + 1*0x20)	/* GDMA ch interrupt pending register */
#define DCON2			(ASIC_BASE+0x50000 + 2*0x20)	/* GDMA ch control register */
#define DSAR2			(ASIC_BASE+0x50004 + 2*0x20)	/* GDMA ch source address register */
#define DDAR2			(ASIC_BASE+0x50008 + 2*0x20)	/* GDMA ch destination address register */
#define DTCR2			(ASIC_BASE+0x5000C + 2*0x20)	/* GDMA ch transfer count register */
#define DRER2			(ASIC_BASE+0x50010 + 2*0x20)	/* GDMA ch run enable register */
#define DIPR2			(ASIC_BASE+0x50014 + 2*0x20)	/* GDMA ch interrupt pending register */
#define DCON3			(ASIC_BASE+0x50000 + 3*0x20)	/* GDMA ch control register */
#define DSAR3			(ASIC_BASE+0x50004 + 3*0x20)	/* GDMA ch source address register */
#define DDAR3			(ASIC_BASE+0x50008 + 3*0x20)	/* GDMA ch destination address register */
#define DTCR3			(ASIC_BASE+0x5000C + 3*0x20)	/* GDMA ch transfer count register */
#define DRER3			(ASIC_BASE+0x50010 + 3*0x20)	/* GDMA ch run enable register */
#define DIPR3			(ASIC_BASE+0x50014 + 3*0x20)	/* GDMA ch interrupt pending register */
#define DCON4			(ASIC_BASE+0x50000 + 4*0x20)	/* GDMA ch control register */
#define DSAR4			(ASIC_BASE+0x50004 + 4*0x20)	/* GDMA ch source address register */
#define DDAR4			(ASIC_BASE+0x50008 + 4*0x20)	/* GDMA ch destination address register */
#define DTCR4			(ASIC_BASE+0x5000C + 4*0x20)	/* GDMA ch transfer count register */
#define DRER4			(ASIC_BASE+0x50010 + 4*0x20)	/* GDMA ch run enable register */
#define DIPR4			(ASIC_BASE+0x50014 + 4*0x20)	/* GDMA ch interrupt pending register */
#define DCON5			(ASIC_BASE+0x50000 + 5*0x20)	/* GDMA ch control register */
#define DSAR5			(ASIC_BASE+0x50004 + 5*0x20)	/* GDMA ch source address register */
#define DDAR5			(ASIC_BASE+0x50008 + 5*0x20)	/* GDMA ch destination address register */
#define DTCR5			(ASIC_BASE+0x5000C + 5*0x20)	/* GDMA ch transfer count register */
#define DRER5			(ASIC_BASE+0x50010 + 5*0x20)	/* GDMA ch run enable register */
#define DIPR5			(ASIC_BASE+0x50014 + 5*0x20)	/* GDMA ch interrupt pending register */

/* Used in DiagCode */
#define DCON(ch)		(ASIC_BASE+0x50000 + ch*0x20)	/* GDMA ch control register */
#define DSAR(ch)		(ASIC_BASE+0x50004 + ch*0x20)	/* GDMA ch source address register */
#define DDAR(ch)		(ASIC_BASE+0x50008 + ch*0x20)	/* GDMA ch destination address register */
#define DTCR(ch)		(ASIC_BASE+0x5000C + ch*0x20)	/* GDMA ch transfer count register */
#define DRER(ch)		(ASIC_BASE+0x50010 + ch*0x20)	/* GDMA ch run enable register */
#define DIPR(ch)		(ASIC_BASE+0x50014 + ch*0x20)	/* GDMA ch interrupt pending register */

/* ----------------------------------------------------------------------------- */
/* Console UART Control Registers     (0xF0060000 ~ 0xF006FFFF)					*/
/* ----------------------------------------------------------------------------- */

#define CUCON			(ASIC_BASE+0x60000)  /* Console UART control register */
#define CUSTAT			(ASIC_BASE+0x60004)  /* Console UART status register */
#define CUINT			(ASIC_BASE+0x60008)  /* Console UART interrupt enable register */
#define CUTXBUF			(ASIC_BASE+0x6000c)  /* Console UART transmit data register */
#define CURXBUF			(ASIC_BASE+0x60010)  /* Console UART receive data register */
#define CUBRD			(ASIC_BASE+0x60014)  /* Console UART baud rate divisor register */
#define CUCHAR1			(ASIC_BASE+0x60018)  /* Console UART control character register1 */
#define CUCHAR2			(ASIC_BASE+0x6001c)  /* Console UART control character register2 */

/* Used in DiagCode */
#define UCON			(ASIC_BASE+0x60000)  /* Console UART control register */
#define USTAT			(ASIC_BASE+0x60004)  /* Console UART status register */   
#define UINTEN			(ASIC_BASE+0x60008)  /* Console UART interrupt enable register */
#define UTXDAT			(ASIC_BASE+0x6000c)  /* Console UART transmit data register */ 
#define URXDAT			(ASIC_BASE+0x60010)  /* Console UART receive data register */
#define UBRDIV			(ASIC_BASE+0x60014)  /* Console UART baud rate divisor register */
#define CONCHAR1		(ASIC_BASE+0x60018)  /* Console UART control character register */
#define CONCHAR2		(ASIC_BASE+0x6001c)  /* Console UART control character register */

/* ----------------------------------------------------------------------------- */
/* High-Speed UART Ch 0/1 control Registers (0xF0070000 ~ 0xF008FFFF)			*/
/* ----------------------------------------------------------------------------- */

#define HUCON0			(ASIC_BASE + 0x70000 + 0*0x10000)	/* R/W	High-Speed UART control register */
#define HUSTAT0			(ASIC_BASE + 0x70004 + 0*0x10000)	/* High-Speed UART status register */
#define HUINT0	    	(ASIC_BASE + 0x70008 + 0*0x10000)	/* High-Speed UART interrupt enable register */
#define HUTXBUF0		(ASIC_BASE + 0x7000C + 0*0x10000)	/* High-Speed UART transmit data register */
#define HURXBUF0		(ASIC_BASE + 0x70010 + 0*0x10000)	/* High-Speed UART receive data register */
#define HUBRD0	    	(ASIC_BASE + 0x70014 + 0*0x10000)	/* High-Speed UART baud rate divisor register */
#define HUCHAR10		(ASIC_BASE + 0x70018 + 0*0x10000)	/* High-Speed UART control character register 1 */
#define HUCHAR20		(ASIC_BASE + 0x7001C + 0*0x10000)	/* High-Speed UART control character register 2 */
#define HUABB0			(ASIC_BASE + 0x70100 + 0*0x10000)	/* High-Speed UART autobaud boundary register */
#define HUABT0			(ASIC_BASE + 0x70104 + 0*0x10000)	/* High-Speed UART autobaud table register */

#define HUCON1			(ASIC_BASE + 0x70000 + 1*0x10000)	/* R/W	High-Speed UART control register */
#define HUSTAT1			(ASIC_BASE + 0x70004 + 1*0x10000)	/* High-Speed UART status register */
#define HUINT1	    	(ASIC_BASE + 0x70008 + 1*0x10000)	/* High-Speed UART interrupt enable register */
#define HUTXBUF1		(ASIC_BASE + 0x7000C + 1*0x10000)	/* High-Speed UART transmit data register */
#define HURXBUF1		(ASIC_BASE + 0x70010 + 1*0x10000)	/* High-Speed UART receive data register */
#define HUBRD1	    	(ASIC_BASE + 0x70014 + 1*0x10000)	/* High-Speed UART baud rate divisor register */
#define HUCHAR11		(ASIC_BASE + 0x70018 + 1*0x10000)	/* High-Speed UART control character register 1 */
#define HUCHAR21		(ASIC_BASE + 0x7001C + 1*0x10000)	/* High-Speed UART control character register 2 */
#define HUABB1			(ASIC_BASE + 0x70100 + 1*0x10000)	/* High-Speed UART autobaud boundary register */
#define HUABT1			(ASIC_BASE + 0x70104 + 1*0x10000)	/* High-Speed UART autobaud table register */

/* ----------------------------------------------------------------------------- */
/* DES Control Registers              (0xF0090000 ~ 0xF009FFFF)					*/
/* ----------------------------------------------------------------------------- */

#define DESCON			(ASIC_BASE+0x90000)		/* DES/3DES control register */
#define DESSTA			(ASIC_BASE+0x90004)		/* DES/3DES status register */
#define DESINT			(ASIC_BASE+0x90008)		/* DES/3DES interrupt enable register */
#define DESRUN			(ASIC_BASE+0x9000C)		/* DES/3DES run enable register */
#define DESKEY1L		(ASIC_BASE+0x90010)		/* Key 1 left half */
#define DESKEY1R		(ASIC_BASE+0x90014)		/* Key 1 right half */
#define DESKEY2L		(ASIC_BASE+0x90018)		/* Key 2 left half */
#define DESKEY2R		(ASIC_BASE+0x9001C)		/* Key 2 right half */
#define DESKEY3L		(ASIC_BASE+0x90020)		/* Key 3 left half */
#define DESKEY3R		(ASIC_BASE+0x90024)		/* Key 3 right half */
#define DESIVL			(ASIC_BASE+0x90028)		/* IV left half */
#define DESIVR			(ASIC_BASE+0x9002C)		/* IV right half */
#define DESINFIFO		(ASIC_BASE+0x90030)		/* DES/3DES input FIFO */
#define DESOUTFIFO		(ASIC_BASE+0x90034)		/* DES/3DES output FIFO */

/* ----------------------------------------------------------------------------- */
/* ETHERNET Ch 0/1  Control Registers    (0xF00A0000 ~ 0xF00DFFFF)				*/
/* ----------------------------------------------------------------------------- */
#if 0	/* defined also in MacApi.h */
#define BDMATXCON(ch)	(ASIC_BASE+0xA0000 + ch*0x20000)	/* Buffered DMA transmit control register */
#define BDMARXCON(ch)	(ASIC_BASE+0xA0004 + ch*0x20000)	/* Buffered DMA receive control register */	
#define BDMATXDPTR(ch)	(ASIC_BASE+0xA0008 + ch*0x20000)	/* Transmit buffer descriptor start address */
#define BDMARXDPTR(ch)	(ASIC_BASE+0xA000C + ch*0x20000)	/* Receive buffer descriptor start address */	
#define BTXBDCNT(ch)	(ASIC_BASE+0xA0010 + ch*0x20000)	/* BDMA Tx Buffer descriptor Counter */
#define BRXBDCNT(ch)	(ASIC_BASE+0xA0014 + ch*0x20000)	/* BDMA Rx Buffer descriptor Counter */
#define BMTXINTEN(ch)	(ASIC_BASE+0xA0018 + ch*0x20000)	/* BDMA/MAC Tx Interrupt enable register */
#define BMRXINTEN(ch)	(ASIC_BASE+0xA001C + ch*0x20000)	/* BDMA/MAC Rx Interrupt enable register */
#define BMTXSTAT(ch)	(ASIC_BASE+0xA0020 + ch*0x20000)	/* BDMA/MAC Tx Status register */
#define BMRXSTAT(ch)	(ASIC_BASE+0xA0024 + ch*0x20000)	/* BDMA/MAC Rx Status register */
#define BDMARXLEN(ch)	(ASIC_BASE+0xA0028 + ch*0x20000)	/* Receive Frame Size */
#define CFTXSTATA(ch)	(ASIC_BASE+0xA0030 + ch* 0x2000)	/* Transmit control frame status */
#define MACCON(ch)	(ASIC_BASE+0xB0000 + ch*0x20000)	/* MAC control */
#define CAMCON(ch)	(ASIC_BASE+0xB0004 + ch*0x20000)	/* CAM control */
#define MACTXCON(ch)	(ASIC_BASE+0xB0008 + ch*0x20000)	/* Transmit control */
#define MACTXSTAT(ch)	(ASIC_BASE+0xB000C + ch*0x20000)	/* Transmit status */
#define MACRXCON(ch)	(ASIC_BASE+0xB0010 + ch*0x20000)	/* Receive control */
#define MACRXSTAT(ch)	(ASIC_BASE+0xB0014 + ch*0x20000)	/* Receive status */
#define STADATA(ch)	(ASIC_BASE+0xB0018 + ch*0x20000)	/* Station management data */
#define STACON(ch)	(ASIC_BASE+0xB001C + ch*0x20000)	/* Station management control and address */
#define CAMEN(ch)	(ASIC_BASE+0xB0028 + ch*0x20000)	/* CAM enable */
#define MISSCNT(ch)	(ASIC_BASE+0xB003C + ch*0x20000)	/* Missed error count */
#define PZCNT(ch)	(ASIC_BASE+0xB0040 + ch*0x20000)	/* Pause count */
#define RMPZCNT(ch)	(ASIC_BASE+0xB0044 + ch*0x20000)	/* Remote pause count */

#define CAM(ch)		(ASIC_BASE+0xB0080 + ch*0x20000)		/* CAM content (32 words) Undefined */
#define CAM_Reg(ch,x)	(CAM(ch) + (x*0x4))				/* CAM content (32 words) Undefined */
#else
#define BMTXSTATA	(ASIC_BASE+0xA0020 + 0*0x20000)	/* BDMA/MAC Tx Status register */
#define BMRXSTATA	(ASIC_BASE+0xA0024 + 0*0x20000)	/* BDMA/MAC Rx Status register */

#define BMTXSTATB	(ASIC_BASE+0xA0020 + 1*0x20000)	/* BDMA/MAC Tx Status register */
#define BMRXSTATB	(ASIC_BASE+0xA0024 + 1*0x20000)	/* BDMA/MAC Rx Status register */
#endif
/* ----------------------------------------------------------------------------- */
/* USB Control Registers              (0xF00E0000 ~ 0xF00EFFFF)					*/
/* ----------------------------------------------------------------------------- */

#define USBFA			(ASIC_BASE+0xE0000)		/* USB function address register */
#define USBPM			(ASIC_BASE+0xE0004)		/* USB power management register */
#define USBINTR			(ASIC_BASE+0xE0008)		/* USB interrupt register */
#define USBINTRE		(ASIC_BASE+0xE000C)		/* USB interrupt enable register */
#define USBFN			(ASIC_BASE+0xE0010)		/* USB frame number register */
#define USBDISCONN		(ASIC_BASE+0xE0014)		/* USB disconnect timer register */
#define USBEP0CSR		(ASIC_BASE+0xE0018)		/* USB endpoint 0 common status register */
#define USBEP1CSR		(ASIC_BASE+0xE001C)		/* USB endpoint 1 common status register */
#define USBEP2CSR		(ASIC_BASE+0xE0020)		/* USB endpoint 2 common status register */
#define USBEP3CSR		(ASIC_BASE+0xE0024)		/* USB endpoint 3 common status register */
#define USBEP4CSR		(ASIC_BASE+0xE0028)		/* USB endpoint 4 common status register */
#define USBWCEP0		(ASIC_BASE+0xE0030)		/* USB write count register for endpoint 0 */
#define USBWCEP1		(ASIC_BASE+0xE0034)		/* USB write count register for endpoint 1 */
#define USBWCEP2		(ASIC_BASE+0xE0038)		/* USB write count register for endpoint 2 */
#define USBWCEP3		(ASIC_BASE+0xE003C)		/* USB write count register for endpoint 3 */
#define USBWCEP4		(ASIC_BASE+0xE0040)		/* USB write count register for endpoint 4 */
#define USBEP0			(ASIC_BASE+0xE0080)  	/* USB endpoint 0 FIFO */
#define USBEP1			(ASIC_BASE+0xE0084)		/* USB endpoint 1 FIFO */
#define USBEP2			(ASIC_BASE+0xE0088)		/* USB endpoint 2 FIFO */
#define USBEP3			(ASIC_BASE+0xE008C)		/* USB endpoint 3 FIFO */
#define USBEP4			(ASIC_BASE+0xE0090)		/* USB endpoint 4 FIFO */

/* ----------------------------------------------------------------------------- */
/* IIC Control Registers              (0xF00F0000 ~ 0xF00FFFFF)					*/ 
/* ----------------------------------------------------------------------------- */

#define IICCON			(ASIC_BASE+0xF0000)  /* Control status register */
#define IICBUF			(ASIC_BASE+0xF0004)	/* Shift buffer register */
#define IICPS			(ASIC_BASE+0xF0008)	/* Prescaler register */
#define IICCNT			(ASIC_BASE+0xF000C)	/* Prescaler counter register */
#define IICPND			(ASIC_BASE+0xF0010)	/* Interrupt pending register */

/* ----------------------------------------------------------------------------- */
/* HDLC Ch 0/1/2  Control Registers      (0xF0100000 ~ 0xF012FFFF)				*/
/* ----------------------------------------------------------------------------- */
#define HMODE0 			(ASIC_BASE+0x100000 + 0*0x10000)	/* HDLC mode register */	             
#define HCON0 			(ASIC_BASE+0x100004 + 0*0x10000)	/* HDLC control register */          
#define HSTAT0  		(ASIC_BASE+0x100008 + 0*0x10000)	/* HDLC status register */
#define HINTEN0 		(ASIC_BASE+0x10000c + 0*0x10000)	/* HDLC interrupt enable register */
#define HTXFIFOC0 		(ASIC_BASE+0x100010 + 0*0x10000)	/* HTxFIFO frame continue register */
#define HTXFIFOT0 		(ASIC_BASE+0x100014 + 0*0x10000)	/* HTxFIFO frame terminate register */
#define HRXFIFO0 		(ASIC_BASE+0x100018 + 0*0x10000)	/* HRxFIFO entry register */
#define HBRGTC0			(ASIC_BASE+0x10001c + 0*0x10000)	/* HDLC BRG time constant register */
#define HPRMB0	 		(ASIC_BASE+0x100020 + 0*0x10000)	/* HDLC preamble register */
#define HSAR00 			(ASIC_BASE+0x100024 + 0*0x10000)	/* HDLC station address 0 */
#define HSAR10	 		(ASIC_BASE+0x100028 + 0*0x10000)	/* HDLC station address 1 */
#define HSAR20	 		(ASIC_BASE+0x10002c + 0*0x10000)	/* HDLC station address 2 */
#define HSAR30	 		(ASIC_BASE+0x100030 + 0*0x10000)	/* HDLC station address 3 */
#define HMASK0 			(ASIC_BASE+0x100034 + 0*0x10000)	/* HDLC mask register */
#define HDMATXPTR0		(ASIC_BASE+0x100038 + 0*0x10000)	/* DMA Tx buffer descriptor pointer */
#define HDMARXPTR0		(ASIC_BASE+0x10003c + 0*0x10000)	/* DMA Rx buffer descriptor pointer */
#define HMFLR0 			(ASIC_BASE+0x100040 + 0*0x10000)	/* Maximum frame length register */
#define HRBSR0 			(ASIC_BASE+0x100044 + 0*0x10000)	/* Receive buffer size register */
#define HSYNC0			(ASIC_BASE+0x100048 + 0*0x10000)	/* HDLC Sync Register */
#define TCON0			(ASIC_BASE+0x10004c + 0*0x10000)	/* Transparent Control regiseter */
#define HTXBDCNT0		(ASIC_BASE+0x1000c0 + 0*0x10000)	/* Tx buffer descriptor count register */
#define HRXBDCNT0		(ASIC_BASE+0x1000c4 + 0*0x10000)	/* Rx buffer descriptor count register */
#define HTXMAXBDCNT0	(ASIC_BASE+0x1000c8 + 0*0x10000)	/* Tx buffer descriptor count mask register */
#define HRXMAXBDCNT0	(ASIC_BASE+0x1000cc + 0*0x10000)	/* Rx buffer descriptor count mask register */

#define HMODE1	 		(ASIC_BASE+0x100000 + 1*0x10000)	/* HDLC mode register */	             
#define HCON1 			(ASIC_BASE+0x100004 + 1*0x10000)	/* HDLC control register */          
#define HSTAT1  		(ASIC_BASE+0x100008 + 1*0x10000)	/* HDLC status register */
#define HINTEN1 		(ASIC_BASE+0x10000c + 1*0x10000)	/* HDLC interrupt enable register */
#define HTXFIFOC1 		(ASIC_BASE+0x100010 + 1*0x10000)	/* HTxFIFO frame continue register */
#define HTXFIFOT1 		(ASIC_BASE+0x100014 + 1*0x10000)	/* HTxFIFO frame terminate register */
#define HRXFIFO1 		(ASIC_BASE+0x100018 + 1*0x10000)	/* HRxFIFO entry register */