s3c2510.h

source code of armboot for s3c4510

/* s3c2510.h - SAMSUNG DSL MCU S3C2510 header file */

/*
This file contains I/O address and related constants for the ARM PID board.
*/
#ifndef INCs3c2510h
#define	 INCs3c2510h
#include "config.h"
#ifdef INCLUDE_FLASH
#define FLASH_ADRS		0x80000000 	/* Base address of Flash part */
#define FLASH_WIDTH	2	  		/* 1 byte-wide part */
/*
 * If the assummptions below are not met, the definitions will
 * probably need to be changed appropriately (see FlashMem.c) and then
 * calibrated using timexN.
 */

#define SYS_FLASH_BOARD_DELAY
#define SYS_FLASH_DELAY_SHIFT 0
#define SYS_FLASH_DELAY_ADJ 0
#define SYS_FLASH_DELAY_INCR 7

#endif /* INCLUDE_FLASH */

/*************************************************************************
* SYSTEM CLOCK 
*/

#define CPU_SPEED	166000000	/* CPU clocked at 72 MHz. The timer */

#define MHz 		1000000

#define fMCLK_MHz 	133000000 	/* 133MHz Bus clock, S3C2510 */
#define fMCLK_MHz2	(fMCLK_MHz/2)
#define fMCLK 		(fMCLK_MHz/MHz)

/*************************************************************************
* changes made from here
*/

/*************************************************************************
* S3C2510 SPECIAL REGISTERS 
*
*/
#define ASIC_BASE		0xf0000000

/* ----------------------------------------------------------------------------- */
/* System PLL Control Registers (SYSCFG)								        */
/* ----------------------------------------------------------------------------- */

#define CORE			1
#define BUS				2
#define USB				3
#define PHY				4

#define CPLLREN			0x80000000		/* CPLLCON register enable */
#define SPLLREN     	0x40000000		/* SPLLCON register enable */
#define UPLLREN			0x20000000		/* UPLLCON register enable */
#define PPLLREN    		0x10000000		/* PPLLCON register enable */

#define CPLLRCE			0x08000000		/* CPLL clock enable */
#define SPLLRCE   		0x04000000		/* SPLL clock enable */
#define UPLLRCE			0x02000000		/* UPLL clock enable */
#define PPLLRCE    		0x01000000		/* PPLL clock enable */

#define BIG				0x10000			/* Read only, 0: Little endian, 1: Big */
#define REMAP			0x100			/* 0: Remap disable, 1: Enable */
#define HCLKO_DIS		0x10			/* HCLKO output disable */
										/* 0: Enable always, 1: Enable during SDRAM access */
#define ARB				0x1				/* 0: round robin bus arbitration, 1: Fixed priority */

#define FastBusMode		0x00
#define Sync0BusMode	0x01
#define Sync1BusMode	0x02
#define AsyncBusMode	0x03

/* ----------------------------------------------------------------------------- */
/* Peripheral Clock Disable Registers (PCLKDIS)									*/
/* ----------------------------------------------------------------------------- */

#define GDMA0CLKDIS		(0x1<<0)	   /* GDMA ch 0 clock disable */
#define GDMA1CLKDIS		(0x1<<1)	   /* GDMA ch 1 clock disable */
#define GDMA2CLKDIS		(0x1<<2)	   /* GDMA ch 2 clock disable */
#define GDMA3CLKDIS		(0x1<<3)	   /* GDMA ch 3 clock disable */
#define GDMA4CLKDIS		(0x1<<4)	   /* GDMA ch 4 clock disable */
#define GDMA5CLKDIS		(0x1<<5)	   /* GDMA ch 5 clock disable */

#define MAC0CLKDIS		(0x1<<6)	   /* ETHERC0 clock disable */
#define MAC1CLKDIS		(0x1<<7)	   /* ETHERC1 clock disable */
#define USBCLKDIS		(0x1<<8)	   /* USB	clock disable */
#define CUARTCLKDIS		(0x1<<9)	   /* CUART clock disable */
#define HUART0CLKDIS	(0x1<<10)	   /* HUART clock disable */
#define HUART1CLKDIS	(0x1<<11)	   /* HUART clock disable */

#define TIMER0CLKDIS	(0x1<<12)	   /* TIMER0 clock disable */
#define TIMER1CLKDIS	(0x1<<13)	   /* TIMER1 clock disable */
#define TIMER2CLKDIS	(0x1<<14)	   /* TIMER2 clock disable */
#define TIMER3CLKDIS	(0x1<<15)	   /* TIMER3 clock disable */
#define TIMER4CLKDIS	(0x1<<16)	   /* TIMER4 clock disable */
#define TIMER5CLKDIS	(0x1<<17)	   /* TIMER5 clock disable */

#define WDTCLKDIS		(0x1<<18)	   /* Watch dog timer clock disable */
#define IOPCCLKDIS		(0x1<<19)	   /* IOPC clock disable */
#define IICCCLKDIS		(0x1<<20)	   /* IICC clock disable */
#define DESCLKDIS		(0x1<<21)	   /* DES clock disable */
#define MEMCONCLKDIS	(0x1<<22)	   /* MEMCON clock disable */
#define SDRAMCCLKDIS	(0x1<<23)	   /* SDRAMC clock disable */

#define HDLC0CLKDIS	    (0x1<<24)	   /* HDLC0 clock disable */
#define HDLC1CLKDIS		(0x1<<25)	   /* HDLC1 clock disable */
#define HDLC2CLKDIS		(0x1<<26)	   /* HDLC2 clock disable */
#define IOM2CLKDIS		(0x1<<27)	   /* IOM2 clock disable */

#define SRack   		(0x1<<30)      /* Self-refresh acknowledge ( Read only) */
#define SRreq   		(0x1<<31)      /* Self-refresh request, 1 : Disable, 0: Enable */

#define ALLCLKENABLE	0x0
#define ALLCLKDISABLE	0xCFFFFFFF

/* ----------------------------------------------------------------------------- */
/* SYATEM PROTECTION AREA SETTING (CP15, C6)									*/
/* ----------------------------------------------------------------------------- */
#define	PROTECTBASE_SHIFT			(12)
#define	PROTECTAREA_EN				(0x1)
#define	PROTECTAREA_4KB				(0x0b<<1)
#define	PROTECTAREA_8KB				(0x0c<<1)
#define	PROTECTAREA_16KB			(0x0d<<1)
#define	PROTECTAREA_32KB			(0x0e<<1)
#define	PROTECTAREA_64KB			(0x0f<<1)
#define	PROTECTAREA_128KB			(0x10<<1)
#define	PROTECTAREA_256KB			(0x11<<1)
#define	PROTECTAREA_512KB			(0x12<<1)
#define	PROTECTAREA_1MB				(0x13<<1)
#define	PROTECTAREA_2MB				(0x14<<1)
#define	PROTECTAREA_4MB				(0x15<<1)
#define	PROTECTAREA_8MB				(0x16<<1)
#define	PROTECTAREA_16MB			(0x17<<1)
#define	PROTECTAREA_32MB			(0x18<<1)
#define	PROTECTAREA_64MB			(0x19<<1)
#define	PROTECTAREA_128MB			(0x1a<<1)
#define	PROTECTAREA_256MB			(0x1b<<1)
#define	PROTECTAREA_512MB			(0x1c<<1)
#define	PROTECTAREA_1GB				(0x1d<<1)
#define	PROTECTAREA_2GB				(0x1e<<1)
#define	PROTECTAREA_4GB				(0x1f<<1)

#define PROTECT_AREA0	0x1
#define PROTECT_AREA1	0x2
#define PROTECT_AREA2	0x4
#define PROTECT_AREA3	0x8
#define PROTECT_AREA4	0x10
#define PROTECT_AREA5	0x20
#define PROTECT_AREA6	0x40
#define PROTECT_AREA7	0x80

/* Permission Encoding */
#define NO_ACCESS	0
#define PRIV_ONLY	1
#define USER_READ	2
#define FULL_ACCESS	3

/* ----------------------------------------------------------------------------- */
/* SYATEM Configuration Registers (0xF0000000 ~ 0xF000FFFF)						*/
/* ----------------------------------------------------------------------------- */

#define SYSCFG			(ASIC_BASE+0x0000)    /* System configuration */
#define PDCODE			(ASIC_BASE+0x0004)    /* Product code and revision number */
#define CLKCON			(ASIC_BASE+0x0008)    /* System clock control */		
#define PCLKDIS			(ASIC_BASE+0x000c)    /* Peripheral clock disable */
#define CLKST			(ASIC_BASE+0x0010)    /* Clock Status */
#define HPRIF			(ASIC_BASE+0x0014)    /* AHB bus master fixed priority */
#define HPRIR			(ASIC_BASE+0x0018)    /* AHB bus master round-robin priority */
#define CPLL			(ASIC_BASE+0x001C)    /* Core PLL Configuration */
#define SPLL			(ASIC_BASE+0x0020)    /* System PLL Configuration */
#define UPLL			(ASIC_BASE+0x0024)    /* USB PLL Configuration */
#define PPLL			(ASIC_BASE+0x0028)    /* PHY PLL Configuration */

/* ----------------------------------------------------------------------------- */
/* MEMORY Control Registers    (0xF0010000 ~ 0xF001FFFF)						*/
/* ----------------------------------------------------------------------------- */

#define B0CON			(ASIC_BASE+0x10000)   /* Bank 0 control */
#define B1CON			(ASIC_BASE+0x10004)   /* Bank 1 control */
#define B2CON			(ASIC_BASE+0x10008)   /* Bank 2 control */
#define B3CON			(ASIC_BASE+0x1000C)   /* Bank 3 control */
#define B4CON			(ASIC_BASE+0x10010)   /* Bank 4 control */
#define B5CON			(ASIC_BASE+0x10014)   /* Bank 5 control */
#define B6CON			(ASIC_BASE+0x10018)   /* Bank 6 control */
#define B7CON			(ASIC_BASE+0x1001C)   /* Bank 7 control */
#define MUXBCON			(ASIC_BASE+0x10020)   /* Muxed bus control */
#define WAITCON			(ASIC_BASE+0x10024)   /* Wait control */
#define WDSCON			(ASIC_BASE+0x10028)   /* Bank access after read wait control */

/* ----------------------------------------------------------------------------- */
/* SDRAM  Control Registers    (0xF0020000 ~ 0xF002FFFF)	                    */
/* ----------------------------------------------------------------------------- */

#define CFGREG   		(ASIC_BASE+0x20000)  /* Configuration register 0*/
#define CMDREG			(ASIC_BASE+0x20004)  /* Configuration register 1 */
#define REFREG			(ASIC_BASE+0x20008)	/* Refresh timer register */
#define WBTOREG			(ASIC_BASE+0x2000c)  /* Write buffer time-out register */

/* Used in DiagCode */
#define SDRAMCONFIG0   	CFGREG
#define SDRAMCONFIG1	CMDREG
#define SDRAMREFRESH	REFREG
#define SDRAMWRIEBUF	WBTOREG

/* ----------------------------------------------------------------------------- */
/* GPIO   control Registers           (0xF0030000 ~ 0xF003FFFF)		            */
/* ----------------------------------------------------------------------------- */

#define IOPMODE1		(ASIC_BASE+0x30000)	/* I/O port mode select lower register for PP[0]~PP[31] */
#define IOPMODE2		(ASIC_BASE+0x30004)	/* I/O port mode select upper register for PP[32]~PP[63] */
#define IOPCON1			(ASIC_BASE+0x30008)	/* I/O port select lower register for PP[0]~PP[31] */
#define IOPCON2			(ASIC_BASE+0x3000C)	/* I/O port select lower register for PP[32]~PP[63] */
#define IOPGDMA			(ASIC_BASE+0x30010)	/* I/O port special function register for DMA */
#define IOPEXTINT		(ASIC_BASE+0x30014)	/* I/O port special function register for external interrupt */
#define IOPEXTINTPND		(ASIC_BASE+0x30018)	/* External Interrupt clear register */
#define IOPDATA1		(ASIC_BASE+0x3001C)	/* I/O port data register */
#define IOPDATA2		(ASIC_BASE+0x30020)	/* I/O port data register */
#define IOPDRV1			(ASIC_BASE+0x30024)	/* I/O port drive control register */
#define IOPDRV2			(ASIC_BASE+0x30028)	/* I/O port drive control register */

/* ----------------------------------------------------------------------------- */
/* TIMER  Control Registers           (0xF0040000 ~ 0xF004FFFF) 		        */
/* ----------------------------------------------------------------------------- */

#define TIMER_TMOD				(ASIC_BASE+0x40000)	/* Timer mode register */
#define TIMER_TIC				(ASIC_BASE+0x40004)	/* Timer Interrupt Clear */
#define TIMER_WDT				(ASIC_BASE+0x40008)	/* Watchdog Timer Register */
#define TIMER_TDATA_0			(ASIC_BASE+0x40010)	/* Timer0 data register */
#define TIMER_TCNT_0			(ASIC_BASE+0x40014)	/* Timer0 counter register */
#define TIMER_TDATA_1			(ASIC_BASE+0x40018)	/* Timer1 data register */
#define TIMER_TCNT_1			(ASIC_BASE+0x4001c)	/* Timer1 counter register */
#define TIMER_TDATA_2			(ASIC_BASE+0x40020)	/* Timer2 data register */
#define TIMER_TCNT_2			(ASIC_BASE+0x40024)	/* Timer2 counter register */
#define TIMER_TDATA_3			(ASIC_BASE+0x40028)	/* Timer3 data register */
#define TIMER_TCNT_3			(ASIC_BASE+0x4002c)	/* Timer3 counter register */
#define TIMER_TDATA_4			(ASIC_BASE+0x40030)	/* Timer4 data register */