📄 s5n8947.h
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#define rTpa1 (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */#define rTacc1 (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */ /* 0x4=5Cycle, 0x5=6Cycle */ /* 0x6=7Cycle, 0x7=Reserved */#define rROMCON1 (ROMEndPtr1|ROMBasePtr1|rTacc1|rTpa1|PMC1)/*---------------------------------------*//*-> ROMCON2 : ROM Bank2 Control register*//*---------------------------------------*/#define ROMBasePtr2 (0x380 << 10) /*=0x03800000 */#define ROMEndPtr2 (0x390 << 20) /*=0x03900000 */#define PMC2 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */ /* 0x2=8Word Page, 0x3=16Word Page */#define rTpa2 (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */#define rTacc2 (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */ /* 0x4=5Cycle, 0x5=6Cycle */ /* 0x6=7Cycle, 0x7=Reserved */#define rROMCON2 (ROMEndPtr2|ROMBasePtr2|rTacc2|rTpa2|PMC2)/*---------------------------------------*//*-> ROMCON3 : ROM Bank3 Control register*//*---------------------------------------*/#define ROMBasePtr3 (0x390 << 10) /*=0x03900000 */#define ROMEndPtr3 (0x3A0 << 20) /*=0x03A00000 */#define PMC3 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */ /* 0x2=8Word Page, 0x3=16Word Page */#define rTpa3 (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */#define rTacc3 (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */ /* 0x4=5Cycle, 0x5=6Cycle */ /* 0x6=7Cycle, 0x7=Reserved */#define rROMCON3 (ROMEndPtr3|ROMBasePtr3|rTacc3|rTpa3|PMC3)/*---------------------------------------*//*-> ROMCON4 : ROM Bank4 Control register*//*---------------------------------------*/#define ROMBasePtr4 (0x3A0 << 10) /*=0x03A00000 */#define ROMEndPtr4 (0x3B0 << 20) /*=0x03B00000 */#define PMC4 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */ /* 0x2=8Word Page, 0x3=16Word Page */#define rTpa4 (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */#define rTacc4 (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */ /* 0x4=5Cycle, 0x5=6Cycle */ /* 0x6=7Cycle, 0x7=Reserved */#define rROMCON4 (ROMEndPtr4|ROMBasePtr4|rTacc4|rTpa4|PMC4)/*---------------------------------------*//*-> ROMCON5 : ROM Bank5 Control register*//*---------------------------------------*/#define ROMBasePtr5 (0x3B0 << 10) /*=0x03B00000 */#define ROMEndPtr5 (0x3C0 << 20) /*=0x03C00000 */#define PMC5 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */ /* 0x2=8Word Page, 0x3=16Word Page */#define rTpa5 (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */#define rTacc5 (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */ /* 0x2=3Cycle, 0x3=4Cycle */ /* 0x4=5Cycle, 0x5=6Cycle */ /* 0x6=7Cycle, 0x7=Reserved */#define rROMCON5 (ROMEndPtr5|ROMBasePtr5|rTacc5|rTpa5|PMC5)/*20070910 by hill#define rROMCON1 0x00000060#define rROMCON2 0x00000060#define rROMCON3 0x00000060#define rROMCON4 0x00000060#define rROMCON5 0x00000060*/#define DRAMBasePtr0 ((ASIC_ROM_BASE_ADDR >> 16) << 10)#define DRAMEndPtr0 (((ASIC_ROM_BASE_ADDR+ASIC_DRAM_SIZE) >> 16) << 20)#define SRAS2CASDelay0 1 /*(Trc)0=1cycle,1=2cycle */#define SRASPrechargeTime0 1 /*(Trp)0=1cycle ~ 3=4clcyle */#define SNoColumnAddr0 0 /*0=8bit,1=9bit,2=10bit,3=11bits */#define SCAN0 (SNoColumnAddr0 << 30)#define STrc0 (SRAS2CASDelay0 << 7)#define STrp0 (SRASPrechargeTime0 << 8)//#define rSDRAMCON0 SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0#define Reserved 1<<4 /*hill add 2007-10-12*/#define mapDRAMBasePtr0 ((ASIC_DRAM_BASE_ADDR >> 16) << 10)#define mapDRAMEndPtr0 (((ASIC_DRAM_BASE_ADDR+ASIC_DRAM_SIZE) >> 16) << 20)//#define maprSDRAMCON0 SCAN0+mapDRAMEndPtr0+mapDRAMBasePtr0+STrp0+STrc0//-----------------------------------------------------------------------------// Configuration of DRAM Bank//-----------------------------------------------------------------------------#if defined(SD16MB) && defined(SD2BANK) && defined(SD32BIT)#define rSDRAMCON0_R 0x18040380#define rSDRAMCON0_B 0x08000380#define rSDRAMCON1_R 0x20060380#define rSDRAMCON1_B 0x10020380#endif#if defined(SD16MB) && defined(SD1BANK) && defined(SD32BIT)#define rSDRAMCON0_R (SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0+Reserved)//0x20040380 /*base : 0x01000000,end : 0x02000000-1*/#define rSDRAMCON0_B (SCAN0+mapDRAMEndPtr0+mapDRAMBasePtr0+STrp0+STrc0+Reserved)//0x10000380 /*base : 0x00000000,end : 0x01000000-1*/#define rSDRAMCON1_R 0x00000000#define rSDRAMCON1_B 0x00000000#endif#if defined(SD16MB) && defined(SD2BANK) && defined(SD16BIT)#define rSDRAMCON0_R 0x58040380#define rSDRAMCON0_B 0x48000380#define rSDRAMCON1_R 0x60060380#define rSDRAMCON1_B 0x50020380#endif#if defined(SD16MB) && defined(SD1BANK) && defined(SD16BIT)#define rSDRAMCON0_R 0x60040380#define rSDRAMCON0_B 0x50000380#define rSDRAMCON1_R 0x0#define rSDRAMCON1_B 0x0#endif#if defined(SD8MB) && defined(SD32BIT)#define rSDRAMCON0_R 0x18040380#define rSDRAMCON0_B 0x08000380#define rSDRAMCON1_R 0x0#define rSDRAMCON1_B 0x0#endif#if defined(SD8MB) && defined(SD16BIT)#define rSDRAMCON0_R 0x58040380#define rSDRAMCON0_B 0x48000380#define rSDRAMCON1_R 0x0#define rSDRAMCON1_B 0x0#endif/*----------------------------------------*//*-> DRAMCON1 : RAM Bank1 control register*//*----------------------------------------*/#define DRAMBasePtr1 (0x300 << 10) /*=0x03000000 */#define DRAMEndPtr1 (0x310 << 20) /*=0x03100000 */#define SRAS2CASDelay1 1 /*(Trc)0=1cycle,1=2cycle */#define SRASPrechargeTime1 1 /*(Trp)0=1cycle ~ 3=4clcyle */#define SNoColumnAddr1 0 /*0=8bit,1=9bit,2=10bit,3=11bits */#define SCAN1 (SNoColumnAddr1 << 30)#define STrc1 (SRAS2CASDelay1 << 7)#define STrp1 (SRASPrechargeTime1 << 8)//#define rSDRAMCON1 (SCAN1|DRAMEndPtr1|DRAMBasePtr1|STrp1|STrc1)/*----------------------------------------*//*-> DRAMCON2 : RAM Bank2 control register*//*----------------------------------------*/#define DRAMBasePtr2 (0x310 << 10) /*=0x03100000 */#define DRAMEndPtr2 (0x320 << 20) /*=0x03200000 */#define SRAS2CASDelay2 1 /*(Trc)0=1cycle,1=2cycle */#define SRASPrechargeTime2 1 /*(Trp)0=1cycle ~ 3=4clcyle */#define SNoColumnAddr2 0 /*0=8bit,1=9bit,2=10bit,3=11bits */#define SCAN2 (SNoColumnAddr2 << 30)#define STrc2 (SRAS2CASDelay2 << 7)#define STrp2 (SRASPrechargeTime2 << 8)#define rSDRAMCON2 (SCAN2|DRAMEndPtr2|DRAMBasePtr2|STrp2|STrc2)/*----------------------------------------*//*-> DRAMCON3 : RAM Bank3 control register*//*----------------------------------------*/#define DRAMBasePtr3 (0x320 << 10) /*=0x03200000 */#define DRAMEndPtr3 (0x330 << 20) /*=0x03300000 */#define SRAS2CASDelay3 1 /*(Trc)0=1cycle,1=2cycle */#define SRASPrechargeTime3 1 /*(Trp)0=1cycle ~ 3=4clcyle */#define SNoColumnAddr3 0 /*0=8bit,1=9bit,2=10bit,3=11bits */#define SCAN3 (SNoColumnAddr3 << 30)#define STrc3 (SRAS2CASDelay3 << 7)#define STrp3 (SRASPrechargeTime3 << 8)#define rSDRAMCON3 (SCAN3|DRAMEndPtr3|DRAMBasePtr3|STrp3|STrc3)/*#define rSDRAMCON2 0x00000000#define rSDRAMCON3 0x00000000*///#define rREFEXTCON 0xCE27E360/*20070910 by hill*///#define rREFEXTCON 0xCE278360#define ExtIOBase (ASIC_EXTIO_BASE_ADDR >> 16) /*Ext IO base address */#define RefEnVSF 0x18000 /*Refresh enable, VSF=1 */#define SRefCycle 8 /*Unit [us], 4k refresh 64ms */#define ROWcycleTime 3 /*0=1cycle, 1=2cycle, 2=3cycle, */ /*3=4cycle, 4=5cycle, */#define SRefCycleValue ((2048+1-(SRefCycle*fMCLK)) << 21)#define STrc (ROWcycleTime << 17)#define rREFEXTCON (SRefCycleValue+STrc+RefEnVSF+ExtIOBase)#define MAX_ISR_HANDLERS 21#define INT_NUM_LEVELS 22#define INT_CSR_MASK 0x003fffff #define INT_MODE_IRQ 0x00#define INT_DISABLE 0x003fffff#define INT_ENABLE 0x00000000//// Interrupt vector for each device//#define INT_LVL_EXTINT0 0 /* External Interrupt0 */#define INT_LVL_EXTINT1 1 /* External Interrupt1 */#define INT_LVL_EXTINT2 2 /* External Interrupt2 */#define INT_LVL_EXTINT3 3 /* External Interrupt3 */#define INT_LVL_UARTTX0 4 /* UART 0 Transmit Interrupt */#define INT_LVL_UARTRX0 5 /* UART 0 Receive & Error Interrupt */#define INT_LVL_UARTTX1 6 /* UART 0 Transmit Interrupt */#define INT_LVL_UARTRX1 7 /* UART 0 Receive & Error Interrupt */#define INT_LVL_GDMA0 8 /* GDMA channel 0 interrupt*/#define INT_LVL_GDMA1 9 /* GDMA channel 1 interrupt */#define INT_LVL_TIMER0 10 /* Timer 0 Interrupt */#define INT_LVL_TIMER1 11 /* Timer 1 Interrupt */#define INT_LVL_HDLC_A_TX 12#define INT_LVL_HDLC_A_RX 13#define INT_LVL_HDLC_B_TX 14#define INT_LVL_HDLC_B_RX 15#define INT_LVL_BDMA_TX 16#define INT_LVL_BDMA_RX 17#define INT_LVL_MAC_TX 18#define INT_LVL_MAC_RX 19#define INT_LVL_I2C 20#define INT_LVL_GLOBAL 21//// Bits in the ASIC_INT_MASK register//#define MASK_EXT0_INT (0x00000001)#define MASK_EXT1_INT (0x00000001 << VEC_EXT1_INT)#define MASK_EXT2_INT (0x00000001 << VEC_EXT2_INT)#define MASK_EXT3_INT (0x00000001 << VEC_EXT3_INT)#define MASK_UART0_TX_INT (0x00000001 << VEC_UART0_TX_INT)#define MASK_UART0_RX_ERR_INT (0x00000001 << VEC_UART0_RX_ERR_INT)#define MASK_UART1_TX_INT (0x00000001 << VEC_UART1_TX_INT)#define MASK_UART1_RX_ERR_INT (0x00000001 << VEC_UART1_RX_ERR_INT)#define MASK_GDMA0_INT (0x00000001 << VEC_GDMA0_INT)#define MASK_GDMA1_INT (0x00000001 << VEC_GDMA1_INT)#define MASK_TIMER0_INT (0x00000001 << VEC_TIMER0_INT )#define MASK_TIMER1_INT (0x00000001 << VEC_TIMER1_INT )#define MASK_HDLC_A_TX_INT (0x00000001 << VEC_HDLC_A_TX_INT )#define MASK_HDLC_A_RX_INT (0x00000001 << VEC_HDLC_A_RX_INT )#define MASK_HDLC_B_TX_INT (0x00000001 << VEC_HDLC_B_TX_INT )#define MASK_HDLC_B_RX_INT (0x00000001 << VEC_HDLC_B_RX_INT )#define MASK_BDMA_TX_INT (0x00000001 << VEC_BDMA_TX_INT )#define MASK_BDMA_RX_INT (0x00000001 << VEC_BDMA_RX_INT )#define MASK_MAC_TX_INT (0x00000001 << VEC_MAC_TX_INT )#define MASK_MAC_RX_INT (0x00000001 << VEC_MAC_RX_INT )//#define MASK_I2C_INT (0x00000001 << VEC_I2C_INT ) //by hill 20070920//#define MASK_GLOBAL_INT (0x00000001 << VEC_GLOBAL_INT)//by hill 20070920#define MASK_ALL 0x003FFFFF/*********************************************************************************************************** Cache Definitions**/#define NON_CACHE_REGION 0x04000000#define CACHE_ENABLE 0x02#define CACHE_4K 0x00#define WRITE_BUFF 0x04#define TAGRAM 0x11000000/*hill add 2007.09.07*/#define CACHE_SET0_BASE_ADDR 0x10000000 // size == 4KB#define CACHE_SET1_BASE_ADDR 0x10800000 // size == 4KB#define CACHE_TAGRAM_BASE_ADDR 0x11000000 // size == 256 x 4-byte = 1KB#define CACHE_TAGRAM_SIZE 256/*Use UART CLOCK - use UART clk = 1, Internal clk = 0 */#define USE_UART_CLK 0#define SYS_INIT_BASE 0x03FF3010#define VPint *(volatile unsigned int *)#define UARTSTAT0 (VPint(ASIC_BASE+0xd008))#define UART_STAT_TXB_EMPTY 0x40#define UARTTXH0 (VPint(ASIC_BASE+0xd00c))#define UARTRXB0 (VPint(ASIC_BASE+0xd010))/* drsohn end *//*********************************************************//* TIMER MODE REGISTER *//*********************************************************/#define TM0_RUN 0x01 /* Timer 0 enable */#define TM0_TOGGLE 0x02 /* 0, interval mode */#define TM0_INTERVAL 0X00#define TM0_OUT 0x04 /* Timer 0 Initial TOUT0 value */#define TM1_RUN 0x08 /* Timer 1 enable */#define TM1_TOGGLE 0x10 /* 0, interval mode */#define TM1_INTERVAL 0X00#define TM1_OUT 0x20 /* Timer 1 Initial TOUT1 value */#define TIMER0_START() (VPint(TIMER_TMOD) |= TM0_RUN)#define TIMER1_START() do{if(!IF_TIMER1_START()){VPint(TIMER_TMOD) |= TM1_RUN;}}while(0)#define TIMER0_STOP() (VPint(TIMER_TMOD) &= ~((UINT32)TM0_RUN))#define TIMER1_STOP() (VPint(TIMER_TMOD) &= ~((UINT32)TM1_RUN))#define IF_TIMER0_START() (VPint(TIMER_TMOD) & (UINT32)TM0_RUN)#define IF_TIMER1_START() (VPint(TIMER_TMOD) & (UINT32)TM1_RUN)/* This is the number of timer ticks that occur per second. */#define TICKS_PER_SECOND 100#define HZ TICKS_PER_SECOND#define CLOCK_TICK_RATE (fMCLK_MHz/HZ)//-----------------------------------------------------------------------------// Declare function protype//-----------------------------------------------------------------------------/*extern void reset_cpu(ulong addr);extern void intDisable(int vect);*/#endif ⌨️ 快捷键说明
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