s5n8947.h

source code of armboot for s3c4510

/* s3c4510.h - SAMSUNG DSL MCU S5N8947 header file */

/*
This file contains I/O address and related constants for the ARM PID board.
*/
#ifndef INCs3c4510h
#define	 INCs3c4510h

#include "config.h"

#ifdef INCLUDE_FLASH
#define FLASH_ADRS		0x01000000 	/* Base address of Flash part */
//#define FLASH_ADRS		0x80000000 	/* Base address of Flash part */
#define FLASH_WIDTH	2	  		/* 1 byte-wide part */
/*
 * If the assummptions below are not met, the definitions will
 * probably need to be changed appropriately (see FlashMem.c) and then
 * calibrated using timexN.
 */

#define SYS_FLASH_BOARD_DELAY
#define SYS_FLASH_DELAY_SHIFT 	0
#define SYS_FLASH_DELAY_ADJ 		0
#define SYS_FLASH_DELAY_INCR 		7

#endif /* INCLUDE_FLASH */

#define CPU_SPEED	50000000	/* CPU clocked at 50 MHz. The timer */

/*************************************************************************
* changes made from here
*/

/*************************************************************************
* S3C4510 SPECIAL REGISTERS 
*
*/
#define ASIC_BASE  			0x3ff0000

/* Interrupt Control */
#define INT_CNTRL_BASE 		(ASIC_BASE+0x4000) /*Define base of all interrupt */

/*SYSTEM MANAGER REGISTERS */

#define SYSCFG				(ASIC_BASE+0x0000)
#define CLKCON  				(ASIC_BASE+0x3000)
#define EXTACON0  			(ASIC_BASE+0x3008)
#define EXTACON1  			(ASIC_BASE+0x300c)
#define EXTDBWTH  			(ASIC_BASE+0x3010)
#define ROMCON0  			(ASIC_BASE+0x3014)
#define ROMCON1  			(ASIC_BASE+0x3018)
#define ROMCON2  			(ASIC_BASE+0x301c)
#define ROMCON3  			(ASIC_BASE+0x3020)
#define ROMCON4  			(ASIC_BASE+0x3024)
#define ROMCON5  			(ASIC_BASE+0x3028)
#define DRAMCON0  			(ASIC_BASE+0x302C)
#define DRAMCON1  			(ASIC_BASE+0x3030)
#define DRAMCON2  			(ASIC_BASE+0x3034)
#define DRAMCON3  			(ASIC_BASE+0x3038)
#define REFEXTCON 			(ASIC_BASE+0x303C)

/* controller registers */
#define INTMODE 			(ASIC_BASE+0x4000)
#define INTPEND 			(ASIC_BASE+0x4004)
#define INTMASK 			(ASIC_BASE+0x4008)
#define INTPRI0 			(ASIC_BASE+0x400C)
#define INTPRI1 			(ASIC_BASE+0x4010)
#define INTPRI2 			(ASIC_BASE+0x4014)
#define INTPRI3 			(ASIC_BASE+0x4018)
#define INTPRI4 			(ASIC_BASE+0x401C)
#define INTPRI5 			(ASIC_BASE+0x4020)
#define INTOFFSET 		(ASIC_BASE+0x4024)

#define INTPENDPRI 		(ASIC_BASE+0x4028)
#define INTPENDTST 		(ASIC_BASE+0x402c)


#define INTOSET_FIQ 		(ASIC_BASE+0x4030)
#define INTOSET_IRQ 		(ASIC_BASE+0x4034)

/*DMA Register*/
#define GDMACON0				(ASIC_BASE+0xB000)
#define GDMASRC0				(ASIC_BASE+0xB004)
#define GDMADST0				(ASIC_BASE+0xB008)
#define GDMACNT0				(ASIC_BASE+0xB00C)

#define GDMACON1				(ASIC_BASE+0xC000)
#define GDMASRC1				(ASIC_BASE+0xC004)
#define GDMADST1				(ASIC_BASE+0xC008)
#define GDMACNT1				(ASIC_BASE+0xC00C)

 /* I/O Port Interface  */
/*hill change 2007.09.06*/
#define IOPMOD 				(ASIC_BASE+0x5000)
#define IOPCON 				(ASIC_BASE+0x5004)
#define IOPDATA 				(ASIC_BASE+0x5008)

/* IIC Registers */
#define  IICCON   			(ASIC_BASE+0xf000)
#define  IICBUF    		(ASIC_BASE+0xf004)
#define  IICPS   			(ASIC_BASE+0xf008)
#define  IICCNT  			(ASIC_BASE+0xf00c)

/* Timer Registers */
#define TIMER_TMOD		(ASIC_BASE + 0x6000) /* TMOD    (R/W) */
#define TIMER_TDATA_0	(ASIC_BASE + 0x6004) /* TDATA0  (R/W) */
#define TIMER_TDATA_1	(ASIC_BASE + 0x6008) /* TDATA1  (R/W) */
#define TIMER_TCNT_0	(ASIC_BASE + 0x600c) /* TCNT0   (R/W) */
#define TIMER_TCNT_1	(ASIC_BASE + 0x6010) /* TCNT1   (R/W) */

/* UART0 Register */
#define ULCON			(ASIC_BASE + 0xD000)		/*UART Line Control Registers*/
#define UCON				(ASIC_BASE + 0xD004)		/*UART Control Register */
#define USTAT			(ASIC_BASE + 0xD008)	/*UART Status Register */
#define UTXBUF			(ASIC_BASE + 0xD00c)	/*UART Transmit Buffer Register*/
#define URXBUF			(ASIC_BASE + 0xD010)	/*UART Receive Buffer Register*/
#define UBRDIV			(ASIC_BASE + 0xD014)	/*UART Baud Rate Divisor Register*/
#define BRDCNT			(ASIC_BASE + 0xD018)	/*UART Baud Rate Count Register */
#define BRDCLK			(ASIC_BASE + 0xD01c)	/*UART Baud Rate Clock Monitor*/

/*UART1 Register*/
#define ULCON_1			(ASIC_BASE + 0xE000)		/*UART Line Control Registers*/
#define UCON_1			(ASIC_BASE + 0xE004)		/*UART Control Register */
#define USTAT_1			(ASIC_BASE + 0xE008)	/*UART Status Register */
#define UTXBUF_1		(ASIC_BASE + 0xE00c)	/*UART Transmit Buffer Register*/
#define URXBUF_1		(ASIC_BASE + 0xE010)	/*UART Receive Buffer Register*/
#define UBRDIV_1		(ASIC_BASE + 0xE014)	/*UART Baud Rate Divisor Register*/
#define BRDCNT_1		(ASIC_BASE + 0xE018)	/*UART Baud Rate Count Register */
#define BRDCLK_1		(ASIC_BASE + 0xE01c)	/*UART Baud Rate Clock Monitor*/


/* Bit definitions within ULCON0/1 Line Control Register*/
#define DATA_BITS_5        0x00
#define DATA_BITS_6        0x01
#define DATA_BITS_7        0x02
#define DATA_BITS_8        0x03

#define PARITY_NONE 	0x00			/* Set No Parity*/
#define PARITY_ODD 		0x20			/* Set Odd Parity*/
#define PARITY_EVEN		0x28			/* Set Even Parity*/
#define ONE_STOP			0x00			/* One Stop Bit*/
#define TWO_STOP			0x02			/* Two Stop Bit*/
#define WORD_LEN			0x03			/* Set Word Length 8*/

#define INT_CLK				0x00			/* Internal Clock Mode */
#define	EXT_CLK				0x40			/* External Clock Mode */

/* Bit definitions within UCON0/1 Control Register*/
#define UCON_RX						0x01			/* Receive Mode -Interrupt*/
#define UCON_STAT_EN			0x04			/* Status Interrrupt -Enable*/
#define UCON_TX						0x08			/* Transmit Mode-Interrupt*/
#define UCON_TX_DIS				0x01			/* Transmit Interrupt -Disable*/
#define UCON_DSR					0x20			/* Data Set Ready -Enable*/
#define UCON_BREAK				0x40			/* Set Break*/
#define UCON_RX_TX_RESET 	0xe4		/* Rx and Tx Reset */

/* Bit definitions within USTAT0/1 Status Register*/

#define USTAT_DTR_LOW			0x10			/* DTR Enable */
#define USTAT_DTR_HIGH		0x00			/* DTR Disable*/
#define USTAT_TX_READY		0x40	 		/* Transmitter Ready for another char */
#define USTAT_RX_AVAIL		0x20	 		/* Character has arrived*/ 
#define USTAT_OVER_ERR  	0x01			/* Over Run Error*/
#define USTAT_PAR_ERR   	0x02			/* Parity Error*/
#define USTAT_FRAME_ERR 	0x04			/* Frame Error*/ 
#define USTAT_RX_READY  	0x20			/* Receive Data Buffer*/

#ifndef REG_READ
#define REG_READ(reg, result) \
	((result) = *(volatile ulong *)(reg))
#endif /*READ REG*/

#ifndef REG_WRITE
#define REG_WRITE(reg, data) \
	(*((volatile ulong *)(reg)) = (data))
#endif /*WRITE REG*/

/*************************************************************************
*
* DRAM Memory Bank 0 area MAP for Exception vector table 
* and Stack, User code area. 
*
*/
#define DRAM_BASE  				0x0	/* Final start address of DRAM */
#define DRAM_LIMIT 				0x1000000			/* 16MByte */
#define	RESET_DRAM_START	0x1000000	/* Start of DRAM on power-up */
#define	RESET_ROM_START		0x0	/* Start od ROM on power-up */

/****************************************************************************
*
* Format of the Program Status Register 
*/
#define FBit 	 		0x40
#define IBit  	 	0x80
#define LOCKOUT  	0xC0 	/* Interrupt lockout value */
#define LOCK_MSK 	0xC0 	/* Interrupt lockout mask value */
#define MOD_MASK 	0x1F 	/* Processor Mode Mask */
#define UDF_MODE 	0x1B 	/* Undefine Mode(UDF) */
#define ABT_MODE 	0x17 	/* Abort Mode(ABT) */
#define SUP_MODE 	0x13 	/* Supervisor Mode (SVC) */
#define IRQ_MODE 	0x12 	/* Interrupt Mode (IRQ) */
#define FIQ_MODE 	0x11 	/* Fast Interrupt Mode (FIQ) */
#define USR_MODE 	0x10 	/* User Mode(USR) */

/*************************************************************************
* SYSTEM CLOCK 
*/
#define MHz 		 			1000000
#define fMCLK_MHz 			50000000
#define fMCLK 		 		fMCLK_MHz/MHz

/*************************************************************************
* SYSTEM MEMORY CONTROL REGISTER EQU TABLES 
*/

/* SYSCFG Register Value */
#define SYSCONFIG_VAL_EDRAM	0x03ff0000	/* System Configuration Value, EDO RAM */
#define SYSCONFIG_VAL_SDRAM	0xA3ff0000  /* System Configuration Value, SDRAM */

/*External I/O access timing register 0,1*/
//#define rEXTACON0	(0x0E780E78)
//#define rEXTACON1	(0x0E780E78)

#define rEXTACON0	(0x0699FFFF)
#define rEXTACON1	(0x0FFF0FFF)

/*hill add 2007.09.07*/

#define DSR0 (2<<0) // ROM Bank0 
#define DSR1 (0<<2) // 0: Disable, 1: Byte, 2: Half-Word, 3: Word 
#define DSR2 (0<<4)
#define DSR3 (0<<6)
#define DSR4 (0<<8)
#define DSR5 (0<<10)
#define DSD0 (3<<12) // RAM Bank0 
#define DSD1 (0<<14)
#define DSD2 (0<<16)
#define DSD3 (0<<18)
#define DSX0 (0<<20) 
#define DSX1 (2<<22)// EXTIO1 switch 16-bit
#define DSX2 (1<<24)//EXTIO2 module card 8-bit
#define DSX3 (0<<26)
#define rEXTDBWTH (DSR0|DSR1|DSR2|DSR3|DSR4|DSR5 | DSD0|DSD1|DSD2|DSD3 | DSX0|DSX1|DSX2|DSX3)


/* 20020612 by drsohn
#define rEXTDBWTH 	(DSR0+DSR1+DSR2+DSP+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3)
*/
/*
#ifdef SD16BIT
#define rEXTDBWTH		0x0AAAA0BA				// for 16bit sdram access - all banks
#else
#define rEXTDBWTH		0x0FFFF0BA				// all SDRAM banks : 32bit
#define rEXTDBWTH		0x00003002				// enable SDRAM bank0 : 32bit; enable ROM bank0
#endif
*/

#define 	ASIC_DRAM_BASE_ADDR 		0x00000000
#define 	ASIC_ROM_BASE_ADDR   		0x01000000
#define 	ASIC_ROM_0_SIZE	   		0x400000
#define 	ASIC_DRAM_SIZE		   	0X01000000
#define 	ASIC_EXTIO_BASE_ADDR   	0x03600000
#define  	ASIC_SRAM_BASE_ADDR		0x03fe0000
#define	ASIC_SOC_BASE_ADDR		0x03ff0000

/*20070910 by hill*/
//#define rSYSCFG					0xE7FFFFA0	/*s3c4510b,SFR base:0x03ff0000, SRAM base : 0x03fe0000, disable write buffer , no cache*/
//#define rSYSCFG					0xE7ffff80	/*s3c4510b 4K sram,4K cache*/

#define     SDM                (1 << 31)                           /* SDRAM Mode, 0=EDO DRAM, 1=SDRAM */
#define     PD_ID              (1 << 26)                           /* S3C4510X=00001 ; S3C4510b = 11001*/
#define     S_REG_BASE_PTR     ((ASIC_SOC_BASE_ADDR >> 16) << 16)    /* Special register bank base pointer */
#define     I_SRAM_BASE_PTR   ((ASIC_SRAM_BASE_ADDR >> 16) << 6)    /* Internal SRAM base pointer */
#define     CM                 (1 << 4)                            /* Cache Mode, 0=4K sram 4K cache, 1=8K cache, 2=8K sram */
#define     WE                 (1 << 2)                            /* Write buffer Enable, 0=disable, 1=enable */
#define     CE                 (1 << 1)                            /* Cache Enable, 0=disable, 1=enable */
#define     SE                 (0 << 0)                            /* Stall Enable, must be 0 */

#define     rSYSCFG    (SDM | PD_ID | S_REG_BASE_PTR | I_SRAM_BASE_PTR | CM | WE | CE | SE)



/***********************************************************
*
* -> ROMCON0 : ROM Bank0 Control register 
*/

#define  	 ROMBasePtr0    ((ASIC_DRAM_BASE_ADDR >> 16) << 10)
#define    ROMEndPtr0     (((ASIC_DRAM_BASE_ADDR+ASIC_ROM_0_SIZE) >> 16) << 20)
#define    PMC0            	0x0             /* 0x0=Normal ROM, 0x1=4Word Page  */
                                       				 /* 0x2=8Word Page, 0x3=16Word Page */
#define    rTpa0           	(0x0 << 2)      /* 0x0=5Cycle, 0x1=2Cycle          */
                                        				/* 0x2=3Cycle, 0x3=4Cycle          */
#define    rTacc0          	(0x4 << 4)      /* 0x0=Disable, 0x1=2Cycle         */
                                        				/* 0x2=3Cycle, 0x3=4Cycle          */
                                        				/* 0x4=5Cycle, 0x5=6Cycle          */
                                        				/* 0x6=7Cycle, 0x7=Reserved        */

#define    mapROMBasePtr0  ((ASIC_ROM_BASE_ADDR >> 16) << 10)
#define    mapROMEndPtr0   (((ASIC_ROM_BASE_ADDR+ASIC_ROM_0_SIZE) >> 16) << 20)


#if defined(AM29LV320D) || defined(AT49BV321)	/*4M*/
//#define rROMCON0_R		0x040003FF
//#define rROMCON0_B		0x140403FF
/*20070910 by hill*/
#define rROMCON0_R		(ROMBasePtr0 | ROMEndPtr0 |PMC0|rTpa0|rTacc0)//0x04000060	/*base : 0x00000000,end : 0x400000-1*/
#define rROMCON0_B		(mapROMBasePtr0 | mapROMEndPtr0 |PMC0|rTpa0|rTacc0)//0x14040060	/*base : 0x01000000,end : 0x01400000-1*/
#else										/*2M*/
//#define rROMCON0_R		0x020003FF
//#define rROMCON0_B		0x120403FF
#define rROMCON0_R		0x02000060
#define rROMCON0_B		0x12040060
#endif


/*---------------------------------------*/
/*-> ROMCON1 : ROM Bank1 Control register*/
/*---------------------------------------*/
#define   	ROMBasePtr1     (0x380 << 10)   /*=0x03800000                      */
#define   	ROMEndPtr1      (0x390 << 20)   /*=0x03900000                      */
#define    	PMC1            0x0             /* 0x0=Normal ROM, 0x1=4Word Page  */
                                        /* 0x2=8Word Page, 0x3=16Word Page */