mac8947.h

来自「source code of armboot for s3c4510」· C头文件 代码 · 共 1,048 行 · 第 1/2 页

#ifndef	__MAC8947h
#define		__MAC8947h

/* Big endian or little endian big = 1, little = 0 */
#define BIG_ENDIAN			0

/*FOR VxWorks*/
/*#define PACK_RESERVED		(__attribute__((__packed__)))*/
#define PACK_RESERVED

/**********BDMA control registers **************/
//s3c4510 have one DMA Ethernet(BDMA),hill 2007.09.07
#define	BDMA_CHANNELA_BASE			0x03ff000+0x9000
#define	MAC_CHANNELA_BASE			0x03ff000+0xA000

/**********BDMA control registers **************/
#define BDMATXCON 				0x0000
#define BDMARXCON 				0x0004
#define BDMATXPTR 				0x0008
#define BDMARXPTR 				0x000C
#define BDMARXLSZ 				0x0010
#define BDMASTAT				0x0014

#define CAM_Reg(x)     			0x0100 + (x * 0x4)

#define	CAM_BASE				0x0100
#define BDMATXBUF      			0x0200
#define BDMARXBUF      			0x0800

/***********MAC control registers**************/
#define MACCON					0x0000
#define CAMCON					0x0004
#define MACTXCON				0x0008
#define MACTXSTAT				0x000C
#define MACRXCON				0x0010
#define MACRXSTAT				0x0014
#define STADATA					0x0018
#define STACON					0x001C
#define CAMEN					0x0028
#define EMISSCNT				0x003C
#define EPZCNT					0x0040
#define ERMPZCNT				0x0044
#define ETXSTAT					0x0040
#define MACRXDESTR     			0x0064
#define MACRXSTATEM    			0x0090
#define MACRXFIFO      			0x0200

struct FD_TX_CONTROL_PACKED
{
#if BIG_ENDIAN
	ulong reserved_bit:25;
	ulong wa_bit:2;
	ulong a_bit:1;
	ulong l_bit:1;
	ulong t_bit:1;
	ulong c_bit:1;
	ulong p_bit:1;
#else
	ulong p_bit:1;
	ulong c_bit:1;
	ulong t_bit:1;
	ulong l_bit:1;
	ulong a_bit:1;
	ulong wa_bit:2;
	ulong reserved_bit:25;
#endif
}PACK_RESERVED;
typedef struct FD_TX_CONTROL_PACKED FD_TX_CONTROL;

struct FD_TX_FRAMEDATA_PACKED
{
#if BIG_ENDIAN
	ulong o_bit:1;
	ulong frameDataPtr:31;
#else
	ulong frameDataPtr:31;
	ulong o_bit:1;
#endif
}PACK_RESERVED;
typedef struct FD_TX_FRAMEDATA_PACKED FD_TX_FRAME_DATA;

struct FD_TX_STATUS_LENGTH_PACKED
{
#if BIG_ENDIAN
	ulong txHalted:1;
	ulong comp:1;
	ulong txPar:1;
	ulong lateColl:1;
	ulong sqeErr:1;
	ulong ncArr:1;
	ulong deferAl:1;
	ulong underRun:1;
	ulong intTx:1;
	ulong paused:1;
	ulong txDefer:1;
	ulong exColl:1;
	ulong txCollCnt:4;
	ulong frameLength:16;
#else
	ulong frameLength:16;
	ulong txCollCnt:4;
	ulong exColl:1;
	ulong txDefer:1;
	ulong paused:1;
	ulong intTx:1;
	ulong underRun:1;
	ulong deferAl:1;
	ulong ncArr:1;
	ulong sqeErr:1;
	ulong lateColl:1;
	ulong txPar:1;
	ulong comp:1;
	ulong txHalted:1;
#endif
}PACK_RESERVED;
typedef struct FD_TX_STATUS_LENGTH_PACKED FD_TX_STATUS_LENGTH;

struct TRANSMIT_FRAME_DESC_PACKED
{
	FD_TX_FRAME_DATA txFrameData;
	FD_TX_CONTROL txControl;
	FD_TX_STATUS_LENGTH txStatusLength;
	struct TRANSMIT_FRAME_DESC_PACKED *nextTxFrameDesc;
}PACK_RESERVED;
typedef struct TRANSMIT_FRAME_DESC_PACKED TRANSMIT_FRAME_DESC;

struct FD_RX_FRAME_DATA_PACKED
{
#if BIG_ENDIAN
	ulong o_bit:1;
	ulong frameDataPtr:31;
#else
	ulong frameDataPtr:31;
	ulong o_bit:1;
#endif
}PACK_RESERVED;
typedef struct FD_RX_FRAME_DATA_PACKED FD_RX_FRAME_DATA;

struct FD_RX_STATUS_LENGTH_PACKED
{
#if BIG_ENDIAN
	ulong rxHalted:1;
	ulong good:1;
	ulong rxPar:1;
	ulong empty2:1;
	ulong longErr:1;
	ulong overFlow:1;
	ulong crcErr:1;
	ulong alignErr:1;
	ulong rx10Stat:1;
	ulong intRx:1;
	ulong ctlRcv:1;
	ulong empty1:1;
	ulong ovMax:1;
	ulong empty0:3;
	ulong frameLength:16;
#else
	ulong frameLength:16;
	ulong empty0:3;
	ulong ovMax:1;
	ulong empty1:1;
	ulong ctlRcv:1;
	ulong intRx:1;
	ulong rx10Stat:1;
	ulong alignErr:1;
	ulong crcErr:1;
	ulong overFlow:1;
	ulong longErr:1;
	ulong empty2:1;
	ulong rxPar:1;
	ulong good:1;
	ulong rxHalted:1;
#endif
}PACK_RESERVED;
typedef struct FD_RX_STATUS_LENGTH_PACKED FD_RX_STATUS_LENGTH;


struct RECEIVE_FRAME_DESC_PACKED			/* receive frame descriptor */
{
	FD_RX_FRAME_DATA rxFrameData;
	ulong reserved;
	FD_RX_STATUS_LENGTH rxStatusLength;
	struct RECEIVE_FRAME_DESC_PACKED *nextRxFrameDesc;
}PACK_RESERVED;
typedef struct RECEIVE_FRAME_DESC_PACKED RECEIVE_FRAME_DESC;

struct BDMARXCON_PACKED
{
#if BIG_ENDIAN
	ulong reserved_0:14;
	ulong erlyNotifyIntr:1;
	ulong buffEmptyIntr:1;
	ulong reset:1;
	ulong enable:1;
	ulong wordAlign:2;
	ulong big_LittleEndian:1;
	ulong maxSizeOverIntrEnb:1;
	ulong notOwnerIntrEnb:1;
	ulong nullListIntrEnb:1;
	ulong recvFrameIntrEnb:1;
	ulong memAddrsInc_Dec:1;
	ulong stop_skipFrame:1;
	ulong burstSize:5;
#else
	ulong burstSize:5;
	ulong stop_skipFrame:1;
	ulong memAddrsInc_Dec:1;
	ulong recvFrameIntrEnb:1;
	ulong nullListIntrEnb:1;
	ulong notOwnerIntrEnb:1;
	ulong maxSizeOverIntrEnb:1;
	ulong big_LittleEndian:1;
	ulong wordAlign:2;
	ulong enable:1;
	ulong reset:1;
	ulong buffEmptyIntr:1;
	ulong erlyNotifyIntr:1;
	ulong reserved_0:14;
#endif
}PACK_RESERVED;

union UNION_BDMARXCON
{
	struct BDMARXCON_PACKED	rxCon_reg;
	ulong rxCon_resetval;
}PACK_RESERVED;
typedef union UNION_BDMARXCON uBDMARXCON;

struct BDMATXCON_PACKED
{
#if BIG_ENDIAN
	ulong reserved_1:16;
	ulong reset:1;
	ulong enable:1;
	ulong macTxStartLevel:3;
	ulong buffEmptyIntrEnb:1;
	ulong notOwnerIntrEnb:1;
	ulong nullListIntrEnb:1;
	ulong sendCntrlPacketIntrEnb:1;
	ulong reserved_0:1;
	ulong stop_skipFrame:1;
	ulong burstSize:5;
#else
	ulong burstSize:5;
	ulong stop_skipFrame:1;
	ulong reserved_0:1;
	ulong sendCntrlPacketIntrEnb:1;
	ulong nullListIntrEnb:1;
	ulong notOwnerIntrEnb:1;
	ulong buffEmptyIntrEnb:1;
	ulong macTxStartLevel:3;
	ulong enable:1;
	ulong reset:1;
	ulong reserved_1:16;
#endif
}PACK_RESERVED;
union UNION_BDMATXCON
	{
		struct BDMATXCON_PACKED	txCon_reg;
		ulong txCon_resetval;
	}PACK_RESERVED;
typedef union UNION_BDMATXCON uBDMATXCON;


struct BDMARXLSZ_PACKED
{
#if BIG_ENDIAN
	ulong bdmaRxFrameLength:16;
	ulong bdmaRxMaxSize:16;
#else
	ulong bdmaRxMaxSize:16;
	ulong bdmaRxFrameLength:16;
#endif
}PACK_RESERVED;

union UNION_BDMARXLSZ
{
		struct BDMARXLSZ_PACKED	rxLsz_reg;
		ulong rxLsz_resetval;
}PACK_RESERVED;
typedef union UNION_BDMARXLSZ uBDMARXLSZ;


struct BDMASTAT_PACKED
{
#if BIG_ENDIAN
	ulong bdmaTxReserved_1:11;
	ulong bdmaTxBuffEmpty:1;
	ulong bdmaTxReserved_0:1;
	ulong bdmaTxNotOwner:1;
	ulong bdmaTxNullList:1;
	ulong bdmaTxCompleteToSendCntrlPacket:1;
	ulong bdmaRxNumofFrames_Buff:8;
	ulong bdmaRxOneMoreFrame:1;
	ulong bdmaRxReserved:1;
	ulong bdmaRxEarlyNotify:1;
	ulong bdmaRxBuffEmpty:1;
	ulong bdmaRxMaxSizeOver:1;
	ulong bdmaRxNotOwner:1;
	ulong bdmaRxNullList:1;
	ulong bdmaRxDoneEveryRxFrame:1;
#else
	ulong bdmaRxDoneEveryRxFrame:1;
	ulong bdmaRxNullList:1;
	ulong bdmaRxNotOwner:1;
	ulong bdmaRxMaxSizeOver:1;
	ulong bdmaRxBuffEmpty:1;
	ulong bdmaRxEarlyNotify:1;
	ulong bdmaRxReserved:1;
	ulong bdmaRxOneMoreFrame:1;
	ulong bdmaRxNumofFrames_Buff:8;
	ulong bdmaTxCompleteToSendCntrlPacket:1;
	ulong bdmaTxNullList:1;
	ulong bdmaTxNotOwner:1;
	ulong bdmaTxReserved_0:1;
	ulong bdmaTxBuffEmpty:1;
	ulong bdmaTxReserved_1:11;
#endif
}PACK_RESERVED;

union UNION_BDMASTAT
{
		struct BDMASTAT_PACKED	stat_reg;
		ulong stat_resetval;
}PACK_RESERVED;
typedef union UNION_BDMASTAT uBDMASTAT;


struct MACCON_PACKED
{
#if BIG_ENDIAN
	ulong reserved_4:16;
	ulong linkStatus:1;
	ulong reserved_3:1;
	ulong enMissRoll:1;
	ulong mdc_off:1;
	ulong reserved_2:1;
	ulong missRoll:1;
	ulong reserved_1:2;
	ulong loop10:1;
	ulong mii_off:1;
	ulong reserved_0:1;
	ulong macLoop:1;
	ulong fullDup:1;
	ulong swReset:1;
	ulong haltImm:1;
	ulong haltRequest:1;
#else
	ulong haltRequest:1;
	ulong haltImm:1;
	ulong swReset:1;
	ulong fullDup:1;
	ulong macLoop:1;
	ulong reserved_0:1;
	ulong mii_off:1;
	ulong loop10:1;
	ulong reserved_1:2;
	ulong missRoll:1;
	ulong reserved_2:1;
	ulong mdc_off:1;
	ulong enMissRoll:1;
	ulong reserved_3:1;
	ulong linkStatus:1;
	ulong reserved_4:16;
#endif
}PACK_RESERVED;

union UNION_MACCON
{
	struct MACCON_PACKED	macCon_reg;
	ulong macCon_resetval;
}PACK_RESERVED;
typedef union UNION_MACCON uMACCON;

struct CAMCON_PACKED
{
#if BIG_ENDIAN
	ulong reserved_0:27;
	ulong cmpEnable:1;
	ulong negCam:1;
	ulong broadcastAccept:1;
	ulong groupAccept:1;
	ulong stationAccept:1;
#else
	ulong stationAccept:1;
	ulong groupAccept:1;
	ulong broadcastAccept:1;
	ulong negCam:1;
	ulong cmpEnable:1;
	ulong reserved_0:27;
#endif
}PACK_RESERVED;

union UNION_CAMCON
{
	struct CAMCON_PACKED	camCon_reg;
	ulong camCon_resetval;
}PACK_RESERVED;
typedef union UNION_CAMCON uCAMCON;


struct MACTXCON_PACKED
{
#if BIG_ENDIAN
	ulong reserved_0:17;
	ulong enableCompletion:1;
	ulong enableTxParity:1;
	ulong enableLateCollison:1;
	ulong enableExcessCollision:1;
	ulong enableNoCarrier:1;
	ulong enableDeferral:1;
	ulong enableUnderRun:1;
	ulong sqeTestModeEnable:1;
	ulong sendPause:1;
	ulong noDefer:1;
	ulong fastBackOff:1;
	ulong suppressCRC:1;
	ulong suppressPadding:1;
	ulong transmitHaltReq:1;
	ulong transmitEnable:1;
#else
	ulong transmitEnable:1;
	ulong transmitHaltReq:1;
	ulong suppressPadding:1;
	ulong suppressCRC:1;
	ulong fastBackOff:1;
	ulong noDefer:1;
	ulong sendPause:1;
	ulong sqeTestModeEnable:1;
	ulong enableUnderRun:1;
	ulong enableDeferral:1;
	ulong enableNoCarrier:1;
	ulong enableExcessCollision:1;
	ulong enableLateCollison:1;
	ulong enableTxParity:1;
	ulong enableCompletion:1;
	ulong reserved_0:17;
#endif
}PACK_RESERVED;

union UNION_MACTXCON
{
	struct MACTXCON_PACKED	macTxCon_reg;
	ulong macTxCon_resetval;
}PACK_RESERVED;
typedef union UNION_MACTXCON uMACTXCON;



struct MACTXSTAT_PACKED
{
#if BIG_ENDIAN
	ulong reserved_0:16;
	ulong transmissionHalted:1;
	ulong completion:1;
	ulong transmitParityError:1;
	ulong lateCollision:1;
	ulong sqe:1;
	ulong noCarrier:1;
	ulong deferral:1;
	ulong underRun:1;
	ulong intrOnTransmit:1;
	ulong paused:1;
	ulong transmitDeferred:1;
	ulong excessiveCollision:1;
	ulong transmitCollCount:4;
#else
	ulong transmitCollCount:4;
	ulong excessiveCollision:1;
	ulong transmitDeferred:1;
	ulong paused:1;
	ulong intrOnTransmit:1;
	ulong underRun:1;
	ulong deferral:1;
	ulong noCarrier:1;
	ulong sqe:1;
	ulong lateCollision:1;
	ulong transmitParityError:1;
	ulong completion:1;
	ulong transmissionHalted:1;
	ulong reserved_0:16;
#endif
}PACK_RESERVED;

union UNION_MACTXSTAT
{
	struct MACTXSTAT_PACKED	macTxStat_reg;
	ulong macTxStat_resetval;
}PACK_RESERVED;
typedef union UNION_MACTXSTAT uMACTXSTAT;


struct MACRXCON_PACKED
{
#if BIG_ENDIAN
	ulong reserved_2:17;
	ulong enableGood:1;
	ulong enableReceiveParity:1;
	ulong reserved_1:1;
	ulong enableLongError:1;
	ulong enableOverFlow:1;
	ulong enableCRCError:1;
	ulong enableAlignment:1;
	ulong reserved_0:1;
	ulong ignoreCRCValue:1;
	ulong passCtrlPacket:1;
	ulong stripCRCVal:1;
	ulong shortEnable:1;
	ulong longEnable:1;
	ulong receiveHaltReq:1;
	ulong receiveEnable:1;
#else
	ulong receiveEnable:1;
	ulong receiveHaltReq:1;
	ulong longEnable:1;
	ulong shortEnable:1;
	ulong stripCRCVal:1;
	ulong passCtrlPacket:1;
	ulong ignoreCRCValue:1;
	ulong reserved_0:1;
	ulong enableAlignment:1;
	ulong enableCRCError:1;
	ulong enableOverFlow:1;
	ulong enableLongError:1;