platform.c

来自「source code of armboot for s3c4510」· C语言 代码 · 共 389 行

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    soc.c
 *
 * Purpose:
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 * Functions:
 *
 * Revision History:
 *
 */



#if !defined(__DEVICE_H__)
#include "device.h"
#endif
//#include "s3c2510.h"
#include "s5n8947.h"		//modified by hill 20070920

#if !defined(__PLATFORM_H__)
#include "platform.h"
#endif


/****** Misc macros **********************************************************/
// unreference argument macro to supress warnings
#define UNUSE_ARG(x)        do { (x) = (x); } while (0)

/*---------------------  Static Definitions  ------------------------*/

/*---------------------  Static Types  ------------------------------*/

/*---------------------  Static Macros  -----------------------------*/

/*---------------------  Static Classes  ----------------------------*/

/*---------------------  Static Variables  --------------------------*/

/*---------------------  Static Functions  --------------------------*/

/*---------------------  Export Variables  --------------------------*/

/*---------------------  Import Functions  --------------------------*/
//void CPUS_vTrapKernelMode(void);
UINT32 CPUS_u32GetMode(void);
void MMUS_vCacheEnable(void);
void MMUS_vCacheDisable(void);


#define tCOS1                   (0x1 << 16)
#define tACS1                   (0x3 << 19)
#define tCOH1                   (0x2 << 22)
#define tACC1                   (0x3 << 25)
#define tCOS2                   (0x7 << 0)
#define tACS2                   (0x7 << 3)
#define tCOH2                   (0x7 << 6)
#define tACC2                   	(0x7 << 9)
#define IOP_DATA_P0             0x00000001
#define IOP_DATA_P1             0x00000002
#define IOP_DATA_P2             0x00000004
#define IOP_DATA_P3             0x00000008

void PLAT_vInit (void)
{
#if 0
    // Ext IRQ enable
    ASIC_IOP_CON1 &= ~IOP_CON1_G13;             // port13 is used for External Interrupt[5]
    ASIC_IOP_EXTINT |= EXTINT_IRQ5_MODE_LEVEL;  // active low, filtering off, level detection

#ifdef __SWITCH_CPUIF_PCI
    // init pci controller
    PCIBDG_Initialize(); 
#endif

    // turn on CPU active LED
    ASIC_IOP_MODE1 &= ~0x10;   // set GP4 output
    ASIC_IOP_DATA1 &= ~0x10;   // set GP4 low

    // GPIO's port5-12 are input mode, and set to GPIO
    ASIC_IOP_MODE1 |= 0x1FE0;
    ASIC_IOP_CON1 |= (0x1FE0);  // set bit[5-12]=1

    // Switch's port24-25 are input mode, and set to GPIO
    ASIC_IOP_MODE1 |= 0x03000000;
    ASIC_IOP_CON1 |= (0x03000000);  // set bit[24-25]=1
#endif

// Initialize EXTERNAL I/O timing
    ASIC_SYS_EXTACON0 |= (tCOS1 | tACS1 | tCOH1 | tACC1);
    ASIC_SYS_EXTACON1 |= (tCOS2 | tACS2 | tCOH2 | tACC2);

    // Ext IRQ enable
    ASIC_IOP_CON1 |= IOPCON_IRQ0_ENABLE;

    // LED-3 turn off
    ASIC_IOP_MODE1 = IOP_DATA_P0;              // set P0 output
    ASIC_IOP_DATA1= 0;
	
}

/*P1 used for mac reset*/
void  PLAT_vSetMacResetPin (UINT8 u8PinLevel)
{
	//ASIC_IOP_MODE1 &=~0x02;
	ASIC_IOP_MODE1 |=0x02;	//hill 20070920
    	if (u8PinLevel == 0)
	        ASIC_IOP_DATA1 &= ~0x02;
    	else
	        ASIC_IOP_DATA1 |= 0x02;
}

/*P3 used for phy reset*/
void  PLAT_vSetPhyResetPin (UINT8 u8PinLevel)
{
    //ASIC_IOP_MODE1 &= ~0x08;
    ASIC_IOP_MODE1 |= 0x08;	//hill 20070920
    if (u8PinLevel == 0)
        ASIC_IOP_DATA1 &= ~0x08;
    else
        ASIC_IOP_DATA1 |= 0x08;
}


void  PLAT_vBoardReboot (void)
{
#ifndef __OS_LINUX
    // set CPU mode to kernel mode
  //   CPUS_vTrapKernelMode();  // 2006-12-18 Steve commented, function in inita.S  // 2007-2-5 Steve commented
#endif
    // jump to ROM program entry point
//    ( (void (*)())ASIC_ROM_BASE_ADDR )();
}

//
// unit of u16Delay is 1 ms
//
void  PLAT_vDelayLoop (UINT16 u16Delay)
{
    UINT32  u32Delay = u16Delay;
    volatile UINT32  u32Tmp;


    // DON'T change this formula
    u32Delay = u32Delay * 12000;
    while (u32Delay != 0) {
        // assert an IO read cycle for delay
        u32Tmp = ASIC_IOP_DATA1;
        u32Delay--;
    }
}

/*---------------------  Export Definitions  ------------------------*/
#define TMR_TICKS_PER_SEC   100         // clock rate is 100 ticks per second

//typedef void (* PFN_CALLBACK_TIMER)(PVOID);

/*---------------------  Export Types  ------------------------------*/

/*---------------------  Export Macros ------------------------------*/
//
// Calculate the real difference between t1 and t0
// Because t1 maybe wrapped around once. 
// (but assume that never wrapped around twice.)
//
#define TMR_u32Diff(t1, t0)     ((t1 >= t0) ? (t1 - t0) : (0xFFFFFFFF - t0 + t1 + 1))

//
// unit of u32Delay is 10 ms
//
// NOTE: DON'T call this function if interrupt is disabled
//       (e.g. in critical sections, in timer callback functions,
//        in other ISRs...), otherwise the program will be blocked
//
//void  PLAT_vDelay (UINT32 u32Delay)
//{
//   UINT32  u32StampTick = TMR_u32GetSysTick();

//    while (1) {
//        if (TMR_u32Diff(TMR_u32GetSysTick(), u32StampTick) >= u32Delay)
//           break;
 //   }
//}

/* // 2006-12-18 Steve commented, function in inita.S
void SOC_vCacheEnable (void)
{
    UINT32  u32CpuOrgMode;


    u32CpuOrgMode = CPUS_u32GetMode();
    if (u32CpuOrgMode != SVC_MODE) {
        // set CPU mode to kernel mode
        CPUS_vTrapKernelMode();
    }

    MMUS_vCacheEnable();
    
    if (u32CpuOrgMode != SVC_MODE) {
        // back to previous mode
#ifdef __TOOLS_ADS
        __asm {
            MRS     r1, CPSR
            BIC     r1, r1, #MODE_MASK
            ORR     r1, r1, #USR_MODE
            MSR     CPSR_cf, r1
        }
#else
        __asm__ (
            ".equ    MODE_MASK, 0x1F\n\t"
            ".equ    USR_MODE,  0x10\n\t"
            "MRS     r1, CPSR\n\t"
            "BIC     r1, r1, #MODE_MASK\n\t"
            "ORR     r1, r1, #USR_MODE\n\t"
            "MSR     CPSR_cf, r1"
            :
            :
            :"r1"
        );
#endif
    }
}


void PLAT_vCacheDisable (void)
{
    UINT32  u32CpuOrgMode;


    u32CpuOrgMode = CPUS_u32GetMode();
    if (u32CpuOrgMode != SVC_MODE) {
        // set CPU mode to kernel mode
        CPUS_vTrapKernelMode();
    }

    MMUS_vCacheDisable();
    
    if (u32CpuOrgMode != SVC_MODE) {
        // back to previous mode
#ifdef __TOOLS_ADS
        __asm {
            MRS     r1, CPSR
            BIC     r1, r1, #MODE_MASK
            ORR     r1, r1, #USR_MODE
            MSR     CPSR_cf, r1
        }
#else
        __asm__ (
            ".equ    MODE_MASK, 0x1F\n\t"
            ".equ    USR_MODE,  0x10\n\t"
            "MRS     r1, CPSR\n\t"
            "BIC     r1, r1, #MODE_MASK\n\t"
            "ORR     r1, r1, #USR_MODE\n\t"
            "MSR     CPSR_cf, r1"
            :
            :
            :"r1"
        );
#endif
    }
}
*/

void  PLAT_vDma0Enable (void)
{

#ifdef __SWITCH_CPUIF_PCI
		    // do nothing
#else
		// DRQ0, DAK0 enable  
		ASIC_IOP_CON1 |= (IOPCON_DRQ0_ENABLE | IOPCON_DAK0_ENABLE );
		
#endif

}


void  PLAT_vDma1Enable (void)
{
#ifdef __SWITCH_CPUIF_PCI
		    // do nothing
#else
	ASIC_IOP_CON1 |= (IOPCON_DRQ1_ENABLE | IOPCON_DAK1_ENABLE );
#endif
}


void  PLAT_vDma0GenIntr (BOOL bIntrEn)
{

#ifdef __SWITCH_CPUIF_PCI
    UNUSE_ARG(bIntrEn);
    // do nothing
#else

    if (bIntrEn)
        ASIC_GDMA_DCON0 = GDMACON0_DMA_INT_EN;
    else
        ASIC_GDMA_DCON0 = 0;
#endif

}


void  PLAT_vDma1GenIntr (BOOL bIntrEn)
{
    UNUSE_ARG(bIntrEn);
    // do nothing
}


void  PLAT_vDma0TrigRx (PUINT8 pu8Buf, UINT16 u16BufLen, UINT32 u32IoPortAddr)
{

#ifdef __SWITCH_CPUIF_PCI
    UNUSE_ARG(pu8Buf);
    UNUSE_ARG(u16BufLen);
    UNUSE_ARG(u32IoPortAddr);
    // do nothing
#else

    u16BufLen = u16BufLen * 2;  //for arm7 compatible
    ASIC_GDMA_DCON0 |= (GDMACON0_EXTDREQ | GDMACON0_BLOCK| GDMACON0_TX_HALFWORD | GDMACON0_SRC_FIX | GDMACON_ACK_CYCLE_16);
    ASIC_GDMA_DCON0 &= ~(GDMACON0_DST_DIR | GDMACON0_DST_INC);
    ASIC_GDMA_DSAR0 = u32IoPortAddr;                     // Set DMA source pointer
    ASIC_GDMA_DDAR0 = (UINT32)pu8Buf;                    // Set DMA destination pointer
    // Set transfer counter
    ASIC_GDMA_DTCR0 = u16BufLen;
    // let CPU start DMA
    ASIC_GDMA_DRER0 = GDMACON0_RUN;
    
#endif

}


void  PLAT_vDma0TrigTx (PUINT8 pu8Buf, UINT16 u16BufLen, UINT32 u32IoPortAddr)
{

#ifdef __SWITCH_CPUIF_PCI
    UNUSE_ARG(pu8Buf);
    UNUSE_ARG(u16BufLen);
    UNUSE_ARG(u32IoPortAddr);
    // do nothing
#else

    u16BufLen = u16BufLen * 2;  //for arm7 compatible
    ASIC_GDMA_DCON0 |= (GDMACON0_EXTDREQ | GDMACON0_BLOCK | GDMACON0_TX_HALFWORD | GDMACON0_DST_FIX | GDMACON_ACK_CYCLE_16);
    ASIC_GDMA_DCON0 &= ~(GDMACON0_SRC_DIR | GDMACON0_SRC_INC);
    ASIC_GDMA_DSAR0 = (UINT32)pu8Buf;                   // Set DMA source pointer
    ASIC_GDMA_DDAR0 = u32IoPortAddr;                    // Set DMA destination pointer
    // Set transfer counter
    ASIC_GDMA_DTCR0 = u16BufLen;
    // let CPU start DMA
    ASIC_GDMA_DRER0 = GDMACON0_RUN;
#endif

}


void  PLAT_vDma1TrigTx (PUINT8 pu8Buf, UINT16 u16BufLen, UINT32 u32IoPortAddr)
{
    UNUSE_ARG(pu8Buf);
    UNUSE_ARG(u16BufLen);
    UNUSE_ARG(u32IoPortAddr);
    // do nothing
}