isr.h

来自「source code of armboot for s3c4510」· C头文件 代码 · 共 251 行

/*
 * File:    isr.h
 */


#ifndef __ISR_H__
#define __ISR_H__

#if !defined(__TTYPE_H__)
#include "ttype.h"
#endif




/*---------------------  Export Definitions  ------------------------*/

//------------------------------------------------------------------------------------------
// Interrupt Control Registers, 30 Internal Interrupt Sources, 6 External Interrupt Sources
//------------------------------------------------------------------------------------------
/*
#define ASIC_INT_INTMOD     (*VPUINT32 (0xF0000000UL + 0x140000)) // Internal interrupt mode register, (0: IRQ mode, 1: FIQ mode)
#define ASIC_INT_EXTMOD     (*VPUINT32 (0xF0000000UL + 0x140004)) // External interrupt mode register, (0: IRQ mode, 1: FIQ mode)
#define ASIC_INT_INTMASK    (*VPUINT32 (0xF0000000UL + 0x140008)) // Internal Interrupt mask register
#define ASIC_INT_EXTMASK    (*VPUINT32 (0xF0000000UL + 0x14000C)) // External Interrupt mask register
#define ASIC_INT_IPRIORHI   (*VPUINT32 (0xF0000000UL + 0x140010)) // High bits, 35-32 bit, Interrupt by priority register, (0: Non-Pending, 1: Pending)
#define ASIC_INT_IPRIORLO   (*VPUINT32 (0xF0000000UL + 0x140014)) // Low bits, 31-0 bit, Interrupt by priority register, (0: Non-Pending, 1: Pending)
#define ASIC_INT_OFFSET_FIQ (*VPUINT32 (0xF0000000UL + 0x140018)) // FIQ interrupt offset register
#define ASIC_INT_OFFSET_IRQ (*VPUINT32 (0xF0000000UL + 0x14001C)) // IRQ interrupt offset register
#define ASIC_INT_INTPRIOR0  (*VPUINT32 (0xF0000000UL + 0x140020)) // Interrupt priority register 0
#define ASIC_INT_INTPRIOR1  (*VPUINT32 (0xF0000000UL + 0x140024)) // Interrupt priority register 1
#define ASIC_INT_INTPRIOR2  (*VPUINT32 (0xF0000000UL + 0x140028)) // Interrupt priority register 2
#define ASIC_INT_INTPRIOR3  (*VPUINT32 (0xF0000000UL + 0x14002C)) // Interrupt priority register 3
#define ASIC_INT_INTPRIOR4  (*VPUINT32 (0xF0000000UL + 0x140030)) // Interrupt priority register 4
#define ASIC_INT_INTPRIOR5  (*VPUINT32 (0xF0000000UL + 0x140034)) // Interrupt priority register 5
#define ASIC_INT_INTPRIOR6  (*VPUINT32 (0xF0000000UL + 0x140038)) // Interrupt priority register 6
#define ASIC_INT_INTPRIOR7  (*VPUINT32 (0xF0000000UL + 0x14003C)) // Interrupt priority register 7
#define ASIC_INT_INTPRIOR8  (*VPUINT32 (0xF0000000UL + 0x140040)) // Interrupt priority register 8
//  Reserved                0xF0140044
#define ASIC_INT_INTTST     (*VPUINT32 (0xF0000000UL + 0x140048)) // High bits, 35-6bit, Internal interrupt test register
#define ASIC_INT_EXTTST     (*VPUINT32 (0xF0000000UL + 0x14004C)) // Low bits, 5-0 bit, External interrupt test register

// Internal Interrupt vector for each device
#define VEC_WDT_INT         29
#define VEC_TMR5_INT        28
#define VEC_TMR4_INT        27
#define VEC_TMR3_INT        26    
#define VEC_TMR2_INT        25
#define VEC_TMR1_INT        24
#define VEC_TMR0_INT        23
#define VEC_GDMA5_INT       22
#define VEC_GDMA4_INT       21
#define VEC_GDMA3_INT       20
#define VEC_GDMA2_INT       19
#define VEC_GDMA1_INT       18
#define VEC_GDMA0_INT       17
#define VEC_DES_INT         16
#define VEC_EMC1_RX_INT     15
#define VEC_EMC1_TX_INT     14
#define VEC_EMC0_RX_INT     13
#define VEC_EMC0_TX_INT     12
#define VEC_SAR_ERROR_INT   11
#define VEC_SAR_DONE_INT    10
#define VEC_PCI_H_INT       9
#define VEC_USB_F_INT       8
#define VEC_USB_H_INT       7
#define VEC_CUART_RX_INT    6
#define VEC_CUART_TX_INT    5
#define VEC_HUART1_RX_INT   4
#define VEC_HUART1_TX_INT   3
#define VEC_HUART0_RX_INT   2
#define VEC_HUART0_TX_INT   1
#define VEC_I2C_INT         0
    
// Internal Interrupt Musk
#define MASK_WDT_INT        (0x00000001 << VEC_WDT_INT) 
#define MASK_TMR5_INT       (0x00000001 << VEC_TMR5_INT)
#define MASK_TMR4_INT       (0x00000001 << VEC_TMR4_INT)
#define MASK_TMR3_INT       (0x00000001 << VEC_TMR3_INT)
#define MASK_TMR2_INT       (0x00000001 << VEC_TMR2_INT)
#define MASK_TMR1_INT       (0x00000001 << VEC_TMR1_INT)
#define MASK_TMR0_INT       (0x00000001 << VEC_TMR0_INT)
#define MASK_GDMA5_INT      (0x00000001 << VEC_GDMA5_INT)
#define MASK_GDMA4_INT      (0x00000001 << VEC_GDMA4_INT)
#define MASK_GDMA3_INT      (0x00000001 << VEC_GDMA3_INT)
#define MASK_GDMA2_INT      (0x00000001 << VEC_GDMA2_INT)
#define MASK_GDMA1_INT      (0x00000001 << VEC_GDMA1_INT)
#define MASK_GDMA0_INT      (0x00000001 << VEC_GDMA0_INT)
#define MASK_DES_INT        (0x00000001 << VEC_DES_INT)
#define MASK_EMC1_RX_INT    (0x00000001 << VEC_EMC1_RX_INT)
#define MASK_EMC1_TX_INT    (0x00000001 << VEC_EMC1_TX_INT)
#define MASK_EMC0_RX_INT    (0x00000001 << VEC_EMC0_RX_INT)
#define MASK_EMC0_TX_INT    (0x00000001 << VEC_EMC0_TX_INT
#define MASK_SAR_ERROR_INT  (0x00000001 << VEC_SAR_ERROR_INT)
#define MASK_SAR_DONE_INT   (0x00000001 << VEC_SAR_DONE_INT)
#define MASK_PCI_H_INT      (0x00000001 << VEC_PCI_H_INT)
#define MASK_USB_F_INT      (0x00000001 << VEC_USB_F_INT)
#define MASK_USB_H_INT      (0x00000001 << VEC_USB_H_INT)
#define MASK_CUART_RX_INT   (0x00000001 << VEC_CUART_RX_INT)
#define MASK_CUART_TX_INT   (0x00000001 << VEC_CUART_TX_INT)
#define MASK_HUART1_RX_INT  (0x00000001 << VEC_HUART1_RX_INT)
#define MASK_HUART1_TX_INT  (0x00000001 << VEC_HUART1_TX_INT)
#define MASK_HUART0_RX_INT  (0x00000001 << VEC_HUART0_RX_INT)
#define MASK_HUART0_TX_INT  (0x00000001 << VEC_HUART0_TX_INT)
#define MASK_I2C_INT        (0x00000001)
#define INTMASK_ALL         0x3FFFFFFF
    
// Internal Interrupt vector for each device
#define VEC_EXT5_INT        5
#define VEC_EXT4_INT        4
#define VEC_EXT3_INT        3
#define VEC_EXT2_INT        2
#define VEC_EXT1_INT        1
#define VEC_EXT0_INT        0

//#define MASK_GLOBAL_INT     0x80000000
#define MASK_EXT5_INT       (0x00000001 << VEC_EXT5_INT)
#define MASK_EXT4_INT       (0x00000001 << VEC_EXT4_INT)
#define MASK_EXT3_INT       (0x00000001 << VEC_EXT3_INT)
#define MASK_EXT2_INT       (0x00000001 << VEC_EXT2_INT)
#define MASK_EXT1_INT       (0x00000001 << VEC_EXT1_INT)
#define MASK_EXT0_INT       (0x00000001)
#define EXTMASK_ALL         0x8000003F
    
// ASIC_INT_OFFSET_FIQ, ASIC_INT_OFFSET_IRQ
#define INT_OFFSET_NOINT    36

#define INT_OFFSET_WDT      35
#define INT_OFFSET_TMR5     34
#define INT_OFFSET_TMR4     33
#define INT_OFFSET_TMR3     32
#define INT_OFFSET_TMR2     31
#define INT_OFFSET_TMR1     30
#define INT_OFFSET_TMR0     29
#define INT_OFFSET_GDMA5    28
#define INT_OFFSET_GDMA4    27
#define INT_OFFSET_GDMA3    26
#define INT_OFFSET_GDMA2    25
#define INT_OFFSET_GDMA1    24
#define INT_OFFSET_GDMA0    23
#define INT_OFFSET_DES      22
#define INT_OFFSET_EMC1_RX  21
#define INT_OFFSET_EMC1_TX  20
#define INT_OFFSET_EMC0_RX  19
#define INT_OFFSET_EMC0_TX  18
#define INT_OFFSET_SAR_ERR  17
#define INT_OFFSET_SAR_DONE 16
#define INT_OFFSET_PCI_H    15
#define INT_OFFSET_USB_F    14
#define INT_OFFSET_USB_H    13
#define INT_OFFSET_CUART_RX 12
#define INT_OFFSET_CUART_TX 11
#define INT_OFFSET_HURT1_RX 10
#define INT_OFFSET_HURT1_TX 9
#define INT_OFFSET_HURT0_RX 8
#define INT_OFFSET_HURT0_TX 7
#define INT_OFFSET_I2C      6
#define INT_OFFSET_EXT5     5
#define INT_OFFSET_EXT4     4
#define INT_OFFSET_EXT3     3
#define INT_OFFSET_EXT2     2
#define INT_OFFSET_EXT1     1
#define INT_OFFSET_EXT0     0




// F011_0100h - F011_017Fh: BIF SFR (AHB Bus Interface Special Function Registers)
#define ASIC_PCI_PCIINTEN   (*VPUINT32 (0xF0000000UL + 0x110108)) // PCI Interrupt Enable Register
#define ASIC_PCI_PCIINTST   (*VPUINT32 (0xF0000000UL + 0x11010C)) // PCI Interrupt Status Register


//
// Bits in the ASIC_PCI_PCIINTEN register(0x110108)
//
#define PCI_PCIINTEN_PRD            (1<<0)
#define PCI_PCIINTEN_PRA            (1<<1)
#define PCI_PCIINTEN_MFE            (1<<2)
#define PCI_PCIINTEN_MPE            (1<<3)
#define PCI_PCIINTEN_TPE            (1<<4)
#define PCI_PCIINTEN_PME            (1<<5)
#define PCI_PCIINTEN_PMC            (1<<6)
#define PCI_PCIINTEN_PSC            (1<<7)
#define PCI_PCIINTEN_BPA            (1<<8)
#define PCI_PCIINTEN_SER            (1<<9)
#define PCI_PCIINTEN_INA            (1<<10)

#define PCI_PCIINTEN_DM0            (1<<12)
#define PCI_PCIINTEN_DE0            (1<<13)
#define PCI_PCIINTEN_DM1            (1<<14)
#define PCI_PCIINTEN_DE1            (1<<15)
#define PCI_PCIINTEN_AER            (1<<16)
#define PCI_PCIINTEN_BAP            (((UINT32)1)<<31)


//
// Bits in the ASIC_PCI_PCIINTST register
//
#define PCIINTST_ALL_CLR        0xFFFFFFFF
*/
/*---------------------  Export Types  ------------------------------*/

/*---------------------  Export Macros  -----------------------------*/

/*---------------------  Export Classes  ----------------------------*/

/*---------------------  Export Variables  --------------------------*/
//extern PFN_HOOK INTR_apfnIntrHandler[];

/*---------------------  Export Functions  --------------------------*/
//
// Interrupt Handler Function
//

//void IISR_vDummyHandler(void);


//
// Exception Handler Function
//
//void EISR_ExcptHndlr_Undef(PUINT8 pu8RegAdr);
//void EISR_ExcptHndlr_Prefetch(PUINT8 pu8RegAdr);
//void EISR_ExcptHndlr_Abort(PUINT8 pu8RegAdr);
//void EISR_ExcptHndlr_Fiq(void);


// critical section functions
//void INTR_vCriticalSectionEnter(void);
//void INTR_vCriticalSectionLeave(void);
//PFN_HOOK INTR_vGetHandler(UINT8 u8Vector);
//void INTR_vSetHandler(UINT8 u8Vector, PFN_HOOK pfnHandler);

void INTR_vDisable(void);

//void INTR_vInit(void);

void INTR_vSwitchEnable(void);
void INTR_vSwitchDisable(void);
//void INTR_vSwitchDma0Enable(void);
//void INTR_vSwitchDma0Disable(void);

//void CPUS_vTrapKernelMode(void);
UINT32 CPUS_u32GetMode(void);




#endif /* __ISR_H__ */