swsys.h

source code of armboot for s3c4510

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    swsys.h
 *
 * Purpose: Hardware accessing functions related to whole system
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 */


#ifndef __SWSYS_H__
#define __SWSYS_H__

#if !defined(__TTYPE_H__)
#include "ttype.h"
#endif
#if !defined(__SWREG_H__)
#include "swreg.h"
#endif
#if !defined(__DEVICE_H__)
#include "device.h"
#endif

//
// Statistic counter for ISR and CPU_MIB
//
#if 0
struct SIsrCpuCntr {
    // CPU ISR status count
    UINT32  dwChipInitOk;           // Isr for Chip initialization complete
    UINT32  dwIsrLnkChg;            // Isr for New link status changed detected
    UINT32  dwIsrPktRx;             // Isr for New packet for CPU to process
    UINT32  dwIsrPktTxFinish;       // Isr for Packet from CPU received
    UINT32  dwIsrLogTblOverThr;     // Isr for Number of log table entries pending for process is over the threshold
    UINT32  dwIsrMemDmaDone;        // Isr for Memory DMA complete
    UINT32  dwIsrWrPktDmaDone;      // Isr for Packet/Memory DMA write complete
    UINT32  dwIsrRdPktDmaDone;      // Isr for Packet/Memory DMA read complete
    UINT32  dwIsrLogTblFull;        // Isr for Log Table Full Detected
    UINT32  dwIsrBufStarve;         // Isr for Buffer Starvation Detected
    UINT32  dwIsrBSF;               // Isr for Broadcast Storm Filtering Detected

    // CPU Rx/Tx count
    UINT32  dwRxOK;                 // Cpu rx pkt ok
    UINT32  dwRxErr;                // Cpu rx pkt error
    UINT32  dwTxOK;                 // Cpu tx pkt ok
    UINT32  dwTxErr;                // Cpu tx pkt error
    UINT32  dwDropPkt;              // Cpu drop pkt
    UINT32  dwFwdSecurity;          // Pkt fwd to cpu caused by security
    UINT32  dwFwdNonSecurity;       // Pkt fwd to cpu caused by non security

    // PCI count
    UINT32  dwIsrMstrMemRdDone;     // Isr for BS2H embedded memory block read  DMA prefetch Complete
    UINT32  dwIsrMstrMemWrDone;     // Isr for BH2S DMA complete, block write  data are fetched in DMAC
    UINT32  dwIsrMstrMemPostWrDone; // Isr for BH2S DMA post write switch done
};
#endif
//extern struct SIsrCpuCntr g_SIsrCpuCntr;


/*---------------------  Export Definitions  ------------------------*/
enum {
    MEM_MOSYS,
    MEM_CAM,
    MEM_ARTISAN
};

/*---------------------  Export Types  ------------------------------*/

/*---------------------  Export Macros  -----------------------------*/
#define SWSYS_vGetChipVer(pu8Ver)   SWREG_vReadU8(INITCTL_REVISION_ID, pu8Ver)

/*---------------------  Export Classes  ----------------------------*/

/*---------------------  Export Variables  --------------------------*/
//extern PFN_HOOK g_pfnLinkChangeFunc;

#ifdef __SWITCH_CPUIF_PCI
extern UINT32 g_u32SwIoBA;
extern UINT32 g_u32SwMemBA;
#endif

/*---------------------  Export Functions  --------------------------*/
#ifdef __SWITCH_CPUIF_PCI//modified by hill 20070919
void SWSYS_vIsrIntaAss(void);
#endif
void ISR_vSwitch(void);

void SWSYS_vSwitchInit(void);
void SWSYS_vSwitchResetSignal(void);
BOOL SWSYS_bSwitchSramBIST(UINT8 byMemType);
void SWSYS_vSetAutoPollOn(void);
void SWSYS_vSetAutoPollOff(void);

// Board functions
void SWSYS_vBoardInit(void);
void SWSYS_vBoardShutdown (void);

#endif /* __SWSYS_H__ */