device.h

source code of armboot for s3c4510

#define HUBRD_RATE_9600     0x00001B00
#define HUBRD_RATE_19200    0x00000D70
#define HUBRD_RATE_38400    0x000006B0
#define HUBRD_RATE_57600    0x00000470
#define HUBRD_RATE_115200   0x00000230
#define HUBRD_RATE_230400   0x00000110
#define HUBRD_RATE_460800   0x00000080
#define HUBRD_RATE_921600   0x00000040


//--------------------------------------
// DES/3DES Special Registers
//--------------------------------------
#define ASIC_ENC_DESCON     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90000)) // DES/3DES control register
#define ASIC_ENC_DESSTA     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90004)) // DES/3DES status register
#define ASIC_ENC_DESINT     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90008)) // DES/3DES interrupt enable register
#define ASIC_ENC_DESRUN     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9000C)) // DES/3DES run enable register
#define ASIC_ENC_DESKEY1L   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90010)) // Key 1 left half
#define ASIC_ENC_DESKEY1R   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90014)) // Key 1 right half
#define ASIC_ENC_DESKEY2L   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90018)) // Key 2 left half
#define ASIC_ENC_DESKEY2R   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9001C)) // Key 2 right half
#define ASIC_ENC_DESKEY3L   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90020)) // Key 3 left half
#define ASIC_ENC_DESKEY3R   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90024)) // Key 3 right half
#define ASIC_ENC_DESIVL     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90028)) // IV left half
#define ASIC_ENC_DESIVR     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9002C)) // IV right half
#define ASIC_ENC_DESINFIFO  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90030)) // DES/3DES input FIFO
#define ASIC_ENC_DESOUTFIFO (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x90034)) // DES/3DES output FIFO

//--------------------------------------
// ETHERNET 0 Special Registers
//--------------------------------------
#define ASIC_EM_BDMATXCON0  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0000)) // Buffered DMA transmit control register
#define ASIC_EM_BDMARXCON0  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0004)) // Buffered DMA receive control register
#define ASIC_EM_BDMATXDPTR0 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0008)) // Transmit buffer descriptor start address
#define ASIC_EM_BDMARXDPTR0 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA000C)) // Receive buffer descriptor start address
#define ASIC_EM_BTXBDCNT0   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0010)) // BDMA Tx buffer descriptor counter
#define ASIC_EM_BRXBDCNT0   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0014)) // BDMA Rx buffer descriptor counter
#define ASIC_EM_BMTXINTEN0  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0018)) // BDMA/MAC Tx Interrupt enable register
#define ASIC_EM_BMRXINTEN0  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA001C)) // BDMA/MAC Rx Interrupt enable register
#define ASIC_EM_BMTXSTAT0   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0020)) // BDMA/MAC Tx Status register
#define ASIC_EM_BMRXSTAT0   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0024)) // BDMA/MAC Rx Status register
#define ASIC_EM_BDMARXLEN0  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0028)) // Receive Frame Size
//  Reserved                0xF00A002C
#define ASIC_EM_CFTXSTAT0   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xA0030)) // Transmit control frame status

#define ASIC_EM_MACCON0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0000)) // MAC control
#define ASIC_EM_CAMCON0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0004)) // CAM control
#define ASIC_EM_MACTXCON0   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0008)) // Transmit control
#define ASIC_EM_MACTXSTAT0  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB000C)) // Transmit status
#define ASIC_EM_MACRXCON0   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0010)) // Receive control
#define ASIC_EM_MACRXSTAT0  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0014)) // Receive status

#define ASIC_EM_STADATA     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0018)) // Station management data
#define ASIC_EM_STACON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB001C)) // Station management control and address
//  Reserved                0xF00B0020 ~ 0xF00B0024
#define ASIC_EM_CAMEN0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0028)) // CAM enable
//  Reserved                0xF00B002C ~ 0xF00B0038
#define ASIC_EM_MISSCNT0    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB003C)) // Missed error count
#define ASIC_EM_PZCNT0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0040)) // Pause count
#define ASIC_EM_RMPZCNT0    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0044)) // Remote pause count
//  Reserved                0xF00B0048 ~ 0xF00B007C
#define ASIC_EM_CAM0        (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0080)) // CAM content (32 words) 0xF00B0080-0xF00B00FC
#define ASIC_EM_CAM0_REG(x) (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB0080 + (x*0x4))) // CAM content Reg0~31

//--------------------------------------
// ETHERNET 1 Special Registers
//--------------------------------------
#define ASIC_EM_BDMATXCON1  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0000)) // Buffered DMA transmit control register
#define ASIC_EM_BDMARXCON1  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0004)) // Buffered DMA receive control register
#define ASIC_EM_BDMATXDPTR1 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0008)) // Transmit buffer descriptor start address
#define ASIC_EM_BDMARXDPTR1 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC000C)) // Receive buffer descriptor start address
#define ASIC_EM_BTXBDCNT1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0010)) // BDMA Tx buffer descriptor counter
#define ASIC_EM_BRXBDCNT1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0014)) // BDMA Rx buffer descriptor counter
#define ASIC_EM_BMTXINTEN1  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0018)) // BDMA/MAC Tx Interrupt enable register
#define ASIC_EM_BMRXINTEN1  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC001C)) // BDMA/MAC Rx Interrupt enable register
#define ASIC_EM_BMTXSTAT1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0020)) // BDMA/MAC Tx Status register
#define ASIC_EM_BMRXSTAT1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0024)) // BDMA/MAC Rx Status register
#define ASIC_EM_BDMARXLEN1  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0028)) // Receive Frame Size
//  Reserved                0xF00C002C ~ 0xF00C002C
#define ASIC_EM_CFTXSTAT1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC0030)) // Transmit control frame status

#define ASIC_EM_MACCON1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0000)) // MAC control
#define ASIC_EM_CAMCON1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0004)) // CAM control
#define ASIC_EM_MACTXCON1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0008)) // Transmit control
#define ASIC_EM_MACTXSTAT1  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD000C)) // Transmit status
#define ASIC_EM_MACRXCON1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0010)) // Receive control
#define ASIC_EM_MACRXSTAT1  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0014)) // Receive status
//  Reserved                0xF00D0018 ~ 0xF00B0024
#define ASIC_EM_CAMEN1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0028)) // CAM enable
//  Reserved                0xF00D002C ~ 0xF00D0038
#define ASIC_EM_MISSCNT1    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD003C)) // Missed error count
#define ASIC_EM_PZCNT1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0040)) // Pause count
#define ASIC_EM_RMPZCNT1    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0044)) // Remote pause count
//  Reserved                0xF00D0048 ~ 0xF00D007C
#define ASIC_EM_CAM1        (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0080)) // CAM content (32 words) 0xF00D0080-0xF00D00FC
#define ASIC_EM_CAM1_REG(x) (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD0080 + (x*0x4))) // CAM content Reg0~31

//--------------------------------------
// USB Function Registers
//--------------------------------------
#define ASIC_USBF_USBFA     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0000)) // USB function address register
#define ASIC_USBF_USBPM     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0004)) // USB power management register
#define ASIC_USBF_USBINTR   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0008)) // USB interrupt register
#define ASIC_USBF_USBINTRE  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE000C)) // USB interrupt enable register
#define ASIC_USBF_USBFN     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0010)) // USB frame number register
#define ASIC_USBF_USBDISCON (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0014)) // USB disconnect timer register
#define ASIC_USBF_USBEP0CSR (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0018)) // USB endpoint 0 common status register
#define ASIC_USBF_USBEP1CSR (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE001C)) // USB endpoint 1 common status register
#define ASIC_USBF_USBEP2CSR (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0020)) // USB endpoint 2 common status register
#define ASIC_USBF_USBEP3CSR (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0024)) // USB endpoint 3 common status register
#define ASIC_USBF_USBEP4CSR (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0028)) // USB endpoint 4 common status register
//  Reserved                0xF00E002C
#define ASIC_USBF_USBWCEP0  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0030)) // USB write count register for endpoint 0
#define ASIC_USBF_USBWCEP1  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0034)) // USB write count register for endpoint 1
#define ASIC_USBF_USBWCEP2  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0038)) // USB write count register for endpoint 2
#define ASIC_USBF_USBWCEP3  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE003C)) // USB write count register for endpoint 3
#define ASIC_USBF_USBWCEP4  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0040)) // USB write count register for endpoint 4
//  Reserved                0xF00E0044 ~ 0xF00E007C
#define ASIC_USBF_USBEP0    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0080)) // USB endpoint 0 FIFO
#define ASIC_USBF_USBEP1    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0084)) // USB endpoint 1 FIFO
#define ASIC_USBF_USBEP2    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0088)) // USB endpoint 2 FIFO
#define ASIC_USBF_USBEP3    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE008C)) // USB endpoint 3 FIFO
#define ASIC_USBF_USBEP4    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE0090)) // USB endpoint 4 FIFO

//--------------------------------------
// I2C Controller Registers
//--------------------------------------
#define ASIC_I2C_IICCON     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xF0000)) // Control status register
#define ASIC_I2C_IICBUF     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xF0004)) // Shift buffer register
#define ASIC_I2C_IICPS      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xF0008)) // Prescaler register
#define ASIC_I2C_IICCNT     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xF000C)) // Prescaler counter register
#define ASIC_I2C_IICPND     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xF0010)) // Interrupt pending register

//--------------------------------------
// USBHOST Controller Registers
//--------------------------------------
#define ASIC_USBHC_REV      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100000)) // HcRevision
#define ASIC_USBHC_CON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100004)) // HcControl
#define ASIC_USBHC_CMDSTAT  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100008)) // HcCommandStatus
#define ASIC_USBHC_INTSTAT  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10000C)) // HcInterruptStatus
#define ASIC_USBHC_INT      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100010)) // HcInterruptEnable
#define ASIC_USBHC_INTDIS   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100014)) // HcInterruptDisable
#define ASIC_USBHC_HCCA     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100018)) // HcHCCA
#define ASIC_USBHC_PRDCURED (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10001C)) // HcPeriodCurrentED
#define ASIC_USBHC_CONHED   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100020)) // HcControlHeadED
#define ASIC_USBHC_CONCURED (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100024)) // HcControlCurrentED
#define ASIC_USBHC_BUKHED   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100028)) // HcBulkHeadED
#define ASIC_USBHC_BUKCURED (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10002C)) // HcBulkCurrentED
#define ASIC_USBHC_DONEH    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100030)) // HcDoneHead
#define ASIC_USBHC_FMINTV   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100034)) // HcFmInterval
#define ASIC_USBHC_FMREM    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100038)) // HcFmRemaining
#define ASIC_USBHC_FMNUM    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10003C)) // HcFmNumber
#define ASIC_USBHC_PRDSTA   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100040)) // HcPeriodicStart
#define ASIC_USBHC_LSTHOD   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100044)) // HcLSThreshold
#define ASIC_USBHC_RHDESPA  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100048)) // HcRhDescriptorA
#define ASIC_USBHC_RHDESPB  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10004C)) // HcRhDescriptorB
#define ASIC_USBHC_RHSTAT   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100050)) // HcRhStatus
#define ASIC_USBHC_RHPSTAT1 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100054)) // HcRhPortStatus1
#define ASIC_USBHC_RHPSTAT2 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x100058)) // HcRhPortStatus2




//----------------------------------------------------------------------------------
// PCI (Mini-PCI) & PC Card Controller
//