📄 device.h
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#define CUCON_IR_MODE 0x00004000 // CUCON[14] When it is '1', infra-red Tx/Rx mode is selected.
#define CUCON_SFEN_ON 0x20000000 // CUCON[29] When it is '1', Console UART will act in software flow control.
#define CUCON_ECHO_ON 0x40000000 // CUCON[30] When it is '1', Rx data is sent not only CURXBUF but also Tx port directly.
// Bits in the ASIC_UART_CUSTAT register
#define CUSTAT_RDV 0x00000001 // CUSTAT[0] Receive Data Valid
#define CUSTAT_BKD 0x00000002 // CUSTAT[1] Break Signal Detected
#define CUSTAT_FER 0x00000004 // CUSTAT[2] Frame Error
#define CUSTAT_PER 0x00000008 // CUSTAT[3] Parity Error
#define CUSTAT_OER 0x00000010 // CUSTAT[4] Overrun Error
#define CUSTAT_CCD 0x00000020 // CUSTAT[5] Control Character Detect
#define CUSTAT_RxIDLE 0x00000800 // CUSTAT[11] Receiver in idle
#define CUSTAT_TxIDLE 0x00020000 // CUSTAT[17] Transmitter in idle
#define CUSTAT_THE 0x00040000 // CUSTAT[18] Transmit Holding Register Empty
// Bits in the ASIC_UART_CUINT register
#define CUIN_RDVIE 0x00000001 // CUINT[0] Receive Data Valid interrupt enable
#define CUIN_BKDIE 0x00000002 // CUINT[1] Break Signal Detected interrupt enable
#define CUIN_FERIE 0x00000004 // CUINT[2] Frame Error interrupt enable
#define CUIN_PERIE 0x00000008 // CUINT[3] Parity Error interrupt enable
#define CUIN_OERIE 0x00000010 // CUINT[4] Overrun Error interrupt enable
#define CUIN_CCDIE 0x00000020 // CUINT[5] Control Character Detect interrupt enable
#define CUIN_TIIE 0x00020000 // CUINT[17] Transmitter Idle interrupt enable
#define CUIN_THEIE 0x00040000 // CUINT[18] Transmit Holding Register Empty interrupt enable
// Baudrate setting in the ASIC_UART_CUBRD when System CLOCK is 133MHz, and Console use PCLK2(PCLK/2) clock source
// BRGOUT = (PCLK2 or EXT_UCLK) / (CNT0+1)*16^CNT1*16
// CUBRD[3:0] Baud rate divisor value CNT1, xxx0 = Divide by 1, xxx1 = Divide by 16
// CUBRD[15:4] Baud rate divisor value CNT0, Time constant value
#define CUBRD_RATE_9600 0x00001B00
#define CUBRD_RATE_19200 0x00000D70
#define CUBRD_RATE_38400 0x000006B0
#define CUBRD_RATE_57600 0x00000470
#define CUBRD_RATE_115200 0x00000230
//--------------------------------------
// High-Speed UART 0 Special Registers
//--------------------------------------
#define ASIC_UART_HU0CON (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x70000)) // High-Speed UART0 control register
#define ASIC_UART_HU0STAT (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x70004)) // High-Speed UART0 status register
#define ASIC_UART_HU0INT (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x70008)) // High-Speed UART0 interrupt enable register
#define ASIC_UART_HU0TXBUF (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x7000C)) // High-Speed UART0 transmit data register (Byte)
#define ASIC_UART_HU0RXBUF (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x70010)) // High-Speed UART0 receive data register (Byte)
#define ASIC_UART_HU0BRD (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x70014)) // High-Speed UART0 baud rate divisor register
#define ASIC_UART_HU0CHAR1 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x70018)) // High-Speed UART0 control character register 1
#define ASIC_UART_HU0CHAR2 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x7001C)) // High-Speed UART0 control character register 2
#define ASIC_UART_HU0ABB (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x70020)) // High-Speed UART0 autobaud boundary register
#define ASIC_UART_HU0ABT (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x70024)) // High-Speed UART0 autobaud table register
//--------------------------------------
// High-Speed UART 1 Special Registers
//--------------------------------------
#define ASIC_UART_HU1CON (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x80000)) // High-Speed UART1 control register
#define ASIC_UART_HU1STAT (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x80004)) // High-Speed UART1 status register
#define ASIC_UART_HU1INT (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x80008)) // High-Speed UART1 interrupt enable register
#define ASIC_UART_HU1TXBUF (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x8000C)) // High-Speed UART1 transmit data register (Byte)
#define ASIC_UART_HU1RXBUF (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x80010)) // High-Speed UART1 receive data register (Byte)
#define ASIC_UART_HU1BRD (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x80014)) // High-Speed UART1 baud rate divisor register
#define ASIC_UART_HU1CHAR1 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x80018)) // High-Speed UART1 control character register 1
#define ASIC_UART_HU1CHAR2 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x8001C)) // High-Speed UART1 control character register 2
#define ASIC_UART_HU1ABB (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x80020)) // High-Speed UART1 autobaud boundary register
#define ASIC_UART_HU1ABT (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x80024)) // High-Speed UART1 autobaud table register
// Bits in the ASIC_UART_HUCON register
#define HUCON_TMODE_MASK 0x00000003 // HUCON[1:0] Transmit mode
#define HUCON_TMODE_DISABLE 0x00000000 // 0: Disable Tx mode
#define HUCON_TMODE_CPUREQ 0x00000001 // 1: CPU request
#define HUCON_TMODE_GDMAREQ 0x00000010 // 2: GDMA request
#define HUCON_RMODE_MASK 0x0000000C // HUCON[3:2] Transmit mode
#define HUCON_RMODE_DISABLE 0x00000000 // 0: Disable Rx mode
#define HUCON_RMODE_CPUREQ 0x00000004 // 1: CPU request
#define HUCON_RMODE_GDMAREQ 0x00000010 // 2: GDMA request,
// (High-speed UART 0 can use only GDMA 0,1,2 channel and, High-speed UART 1 can use only GDMA 3,4,5 channel)
#define HUCON_SBR_ON 0x00000010 // HUCON[4] Set this bit to one to cause the Console UART to send a break.
#define HUCON_SCSEL_EXTUCLK 0x00000020 // HUCON[5] Clock Source: 0 = Internal (PCLK2), 1 = External (EXT_UCLK)
#define HUCON_AUBD_ON 0x00000040 // HUCON[6] Auto Baud Rate Detect
#define HUCON_LOOPB_ON 0x00000080 // HUCON[7] Enable loop-back mode
#define HUCON_PMD_MASK 0x00000700 // HUCON[10:8] Parity mode
#define HUCON_PMD_NONE 0x00000000 // 0xx = No parity.
#define HUCON_PMD_ODD 0x00000400 // 100 = Odd parity.
#define HUCON_PMD_EVEN 0x00000500 // 101 = Even parity.
#define HUCON_PMD_FORCE1 0x00000600 // 110 = Parity forced/checked as 1
#define HUCON_PMD_FORCE0 0x00000700 // 111 = Parity forced/checked as 0
#define HUCON_STB_MASK 0x00000800 // HUCON[11] Number of Stop bits
#define HUCON_STB_ONE 0x00000000 // 0 = One stop bit per frame
#define HUCON_STB_TWO 0x00000800 // 1 = Two stop bit per frame
#define HUCON_WL_MASK 0x00003000 // HUCON[13:12] Number of data bits to be transmitted
#define HUCON_WL_5BIT 0x00000000 // 00 = 5bits
#define HUCON_WL_6BIT 0x00001000 // 01 = 6bits
#define HUCON_WL_7BIT 0x00002000 // 10 = 7bits
#define HUCON_WL_8BIT 0x00003000 // 11 = 8bits
#define HUCON_IR_MODE 0x00004000 // HUCON[14] When it is '1', infra-red Tx/Rx mode is selected.
#define HUCON_TFEN 0x00010000 // HUCON[16] When it is '1', Transmit FIFO enable
#define HUCON_RFEN 0x00020000 // HUCON[17] When it is '1', Receive FIFO enable
#define HUCON_TFRST 0x00040000 // HUCON[18] When it is '1', Transmit FIFO reset
#define HUCON_RFRST 0x00080000 // HUCON[19] When it is '1', Receive FIFO reset
#define HUCON_TFTL_MASK 0x00300000 // HUCON[21:20] Transmit FIFO trigger level
#define HUCON_TFTL_30_32 0x00000000 // 00 = 30-byte empty/32-byte
#define HUCON_TFTL_24_32 0x00100000 // 01 = 24-byte empty/32-byte
#define HUCON_TFTL_16_32 0x00200000 // 10 = 16-byte empty/32-byte
#define HUCON_TFTL_8_32 0x00300000 // 11 = 8-byte empty/32-byte
#define HUCON_RFTL_MASK 0x00C00000 // HUCON[23:22] Receive FIFO trigger level
#define HUCON_RFTL_1_32 0x00000000 // 00 = 1-byte valid/32-byte
#define HUCON_RFTL_8_32 0x00400000 // 01 = 8-byte valid/32-byte
#define HUCON_RFTL_18_32 0x00800000 // 10 = 18-byte valid/32-byte
#define HUCON_RFTL_28_32 0x00C00000 // 11 = 28-byte valid/32-byte
#define HUCON_DTR_LOW 0x01000000 // HUCON[24] Data Terminal Ready to pin,
// Setting to one, the HUnDTR0/HUnDTR1 pin goes to Low level.
#define HUCON_HFEN_ON 0x10000000 // HUCON[28] When it is '1', Hardware Flow Control enable
#define HUCON_SFEN_ON 0x20000000 // HUCON[29] When it is '1', UART will act in software flow control.
#define HUCON_ECHO_ON 0x40000000 // HUCON[30] When it is '1', Rx data is sent not only CURXBUF but also Tx port directly.
#define HUCON_RTR_MODE 0x80000000 // HUCON[31] RTS/RTR selection, 0 = RTS, 1 = RTR
// Bits in the ASIC_UART_HUSTAT register
#define HUSTAT_RDV 0x00000001 // HUSTAT[0] Receive Data Valid
#define HUSTAT_BKD 0x00000002 // HUSTAT[1] Break Signal Detected
#define HUSTAT_FER 0x00000004 // HUSTAT[2] Frame Error
#define HUSTAT_PER 0x00000008 // HUSTAT[3] Parity Error
#define HUSTAT_OER 0x00000010 // HUSTAT[4] Overrun Error
#define HUSTAT_CCD 0x00000020 // HUSTAT[5] Control Character Detect
#define HUSTAT_DCDL 0x00000040 // HUSTAT[6] Data carrier Detect Lost
#define HUSTAT_RFREA 0x00000080 // HUSTAT[7] Receive FIFO Data trigger level reach
#define HUSTAT_RFEMT 0x00000100 // HUSTAT[8] Receive FIFO empty
#define HUSTAT_RFFUL 0x00000200 // HUSTAT[9] Receive FIFO full
#define HUSTAT_RFOV 0x00000400 // HUSTAT[10] Receive FIFO overrun
#define HUSTAT_RxIDLE 0x00000800 // HUSTAT[11] Receiver in idle
#define HUSTAT_E_RxTO 0x00001000 // HUSTAT[12] Receive Event time out
#define HUSTAT_AUBDDN 0x00002000 // HUSTAT[13] AutoBaud Rate Detection Done
#define HUSTAT_DSR 0x00004000 // HUSTAT[14] Data Set ready
#define HUSTAT_CTS 0x00008000 // HUSTAT[15] Clear To Send
#define HUSTAT_E_CTS 0x00010000 // HUSTAT[16] CTS Event occurred
#define HUSTAT_TxIDLE 0x00020000 // HUSTAT[17] Transmitter in idle
#define HUSTAT_THE 0x00040000 // HUSTAT[18] Transmit Holding Register Empty
#define HUSTAT_TFEMT 0x00080000 // HUSTAT[19] Transmit FIFO Empty
#define HUSTAT_TFFUL 0x00100000 // HUSTAT[20] Transmit FIFO full
// Bits in the ASIC_UART_HUINT register
#define HUIN_RDVIE 0x00000001 // HUINT[0] Receive Data Valid interrupt enable
#define HUIN_BKDIE 0x00000002 // HUINT[1] Break Signal Detected interrupt enable
#define HUIN_FERIE 0x00000004 // HUINT[2] Frame Error interrupt enable
#define HUIN_PERIE 0x00000008 // HUINT[3] Parity Error interrupt enable
#define HUIN_OERIE 0x00000010 // HUINT[4] Overrun Error interrupt enable
#define HUIN_CCDIE 0x00000020 // HUINT[5] Control Character Detect interrupt enable
#define HUIN_DCDLIE 0x00000040 // HUINT[6] DCD High at receiver checking time interrupt enable
#define HUIN_RFREAIE 0x00000080 // HUINT[7] Receive FIFO Data trigger level reach interrupt enable
#define HUIN_OVFFIE 0x00000400 // HUINT[10] Receive FIFO overrun interrupt enable
#define HUIN_E_RxTOIE 0x00001000 // HUINT[12] Receive Event time out interrupt enable
#define HUIN_AUBDDNIE 0x00002000 // HUINT[13] AutoBaud Rate Detection done interrupt enable
#define HUIN_E_CTSIE 0x00010000 // HUINT[16] CTS Event occurred interrupt enable
#define HUIN_TIIE 0x00020000 // HUINT[17] Transmitter Idle interrupt enable
#define HUIN_THEIE 0x00040000 // HUINT[18] Transmit Holding Register Empty interrupt enable
// Baudrate setting in the ASIC_UART_CUBRD when System CLOCK is 133MHz, and Console use PCLK2(PCLK/2) clock source
// BRGOUT = (PCLK2 or EXT_UCLK) / (CNT0+1)*16^CNT1*16
// CUBRD[3:0] Baud rate divisor value CNT1, xxx0 = Divide by 1, xxx1 = Divide by 16
// CUBRD[15:4] Baud rate divisor value CNT0, Time constant value
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