device.h

source code of armboot for s3c4510

// Timer Control Registers
//--------------------------------------
#define ASIC_TMR_TMOD       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40000)) // Timer mode register
#define ASIC_TMR_TIC        (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40004)) // Timer Interrupt Clear
#define ASIC_TMR_WDT        (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40008)) // Watchdog Timer Register
//  Reserved                0xF004000C
#define ASIC_TMR_TDATA0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40010)) // Timer 0 data register
#define ASIC_TMR_TCNT0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40014)) // Timer 0 count register

#define ASIC_TMR_TDATA1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40018)) // Timer 1 data register
#define ASIC_TMR_TCNT1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4001C)) // Timer 1 count register

#define ASIC_TMR_TDATA2     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40020)) // Timer 2 data register
#define ASIC_TMR_TCNT2      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40024)) // Timer 2 count register

#define ASIC_TMR_TDATA3     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40028)) // Timer 3 data register
#define ASIC_TMR_TCNT3      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4002C)) // Timer 3 count register

#define ASIC_TMR_TDATA4     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40030)) // Timer 4 data register
#define ASIC_TMR_TCNT4      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40034)) // Timer 4 count register

#define ASIC_TMR_TDATA5     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x40038)) // Timer 5 data register
#define ASIC_TMR_TCNT5      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4003C)) // Timer 5 count register

// Bits in the ASIC_TMR_TMOD register
#define TMOD_TE0            0x00000001  // TMOD[0] Timer 0 enable: 0 = Disable timer0, 1 = Enable timer0
#define TMOD_TMD0_TOGGLE    0x00000002  // TMOD[1] Timer 0 mode: 0 = Interval mode, 1 = Toggle mode
#define TMOD_TCLR0_1        0x00000004  // TMOD[2] Timer 0 initial TOUT0 value, 1 = Initial TOUT0 is 1 in toggle mode

#define TMOD_TE1            0x00000010  // TMOD[4] Timer 1 enable: 0 = Disable timer1, 1 = Enable timer1
#define TMOD_TMD1_TOGGLE    0x00000020  // TMOD[5] Timer 1 mode: 0 = Interval mode, 1 = Toggle mode
#define TMOD_TCLR1_1        0x00000040  // TMOD[6] Timer 1 initial TOUT1 value, 1 = Initial TOUT1 is 1 in toggle mode

#define TMOD_TE2            0x00000100  // TMOD[8] Timer 2 enable: 0 = Disable timer2, 1 = Enable timer2
#define TMOD_TMD2_TOGGLE    0x00000200  // TMOD[9] Timer 2 mode: 0 = Interval mode, 1 = Toggle mode
#define TMOD_TCLR2_1        0x00000400  // TMOD[10] Timer 2 initial TOUT2 value, 1 = Initial TOUT2 is 1 in toggle mode

#define TMOD_TE3            0x00001000  // TMOD[12] Timer 3 enable: 0 = Disable timer3, 1 = Enable timer3
#define TMOD_TMD3_TOGGLE    0x00002000  // TMOD[13] Timer 3 mode: 0 = Interval mode, 1 = Toggle mode
#define TMOD_TCLR3_1        0x00004000  // TMOD[14] Timer 3 initial TOUT3 value, 1 = Initial TOUT3 is 1 in toggle mode

#define TMOD_TE4            0x00001000  // TMOD[16] Timer 4 enable: 0 = Disable timer4, 1 = Enable timer4
#define TMOD_TMD4_TOGGLE    0x00002000  // TMOD[17] Timer 4 mode: 0 = Interval mode, 1 = Toggle mode
#define TMOD_TCLR4_1        0x00004000  // TMOD[18] Timer 4 initial TOUT4 value, 1 = Initial TOUT4 is 1 in toggle mode

#define TMOD_TE5            0x00010000  // TMOD[20] Timer 5 enable: 0 = Disable timer5, 1 = Enable timer5
#define TMOD_TMD5_TOGGLE    0x00020000  // TMOD[21] Timer 5 mode: 0 = Interval mode, 1 = Toggle mode
#define TMOD_TCLR5_1        0x00040000  // TMOD[22] Timer 5 initial TOUT5 value, 1 = Initial TOUT5 is 1 in toggle mode

// Bits in the ASIC_TMR_TIC register
#define TIC_WDTIC           0x00000001  // TIC[0] WDT interrupt clear: 0 = no interrupt clear, 1 = interrupt clear
#define TIC_TIC0            0x00000002  // TIC[1] Timer0 interrupt clear
#define TIC_TIC1            0x00000004  // TIC[2] Timer1 interrupt clear
#define TIC_TIC2            0x00000008  // TIC[3] Timer2 interrupt clear
#define TIC_TIC3            0x00000010  // TIC[4] Timer3 interrupt clear
#define TIC_TIC4            0x00000020  // TIC[5] Timer4 interrupt clear
#define TIC_TIC5            0x00000040  // TIC[6] Timer5 interrupt clear


//--------------------------------------
// GDMA Special Registers
//--------------------------------------
#define ASIC_GDMA_DCON0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50000)) // GDMA channel 0 control register
#define ASIC_GDMA_DSAR0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50004)) // GDMA channel 0 source address register
#define ASIC_GDMA_DDAR0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50008)) // GDMA channel 0 destination address register
#define ASIC_GDMA_DTCR0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5000C)) // GDMA channel 0 transfer count register
#define ASIC_GDMA_DRER0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50010)) // GDMA channel 0 run enable register
#define ASIC_GDMA_DIPR0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50014)) // GDMA channel 0 interrupt pending register
//  Reserved                0xF0050018 ~ 0xF005001C
#define ASIC_GDMA_DCON1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50020)) // GDMA channel 1 control register
#define ASIC_GDMA_DSAR1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50024)) // GDMA channel 1 source address register
#define ASIC_GDMA_DDAR1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50028)) // GDMA channel 1 destination address register
#define ASIC_GDMA_DTCR1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5002C)) // GDMA channel 1 transfer count register
#define ASIC_GDMA_DRER1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50030)) // GDMA channel 1 run enable register
#define ASIC_GDMA_DIPR1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50034)) // GDMA channel 1 interrupt pending register
//  Reserved                0xF0050038 ~ 0xF005003C
#define ASIC_GDMA_DCON2     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50040)) // GDMA channel 2 control register
#define ASIC_GDMA_DSAR2     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50044)) // GDMA channel 2 source address register
#define ASIC_GDMA_DDAR2     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50048)) // GDMA channel 2 destination address register
#define ASIC_GDMA_DTCR2     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5004C)) // GDMA channel 2 transfer count register
#define ASIC_GDMA_DRER2     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50050)) // GDMA channel 2 run enable register
#define ASIC_GDMA_DIPR2     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50054)) // GDMA channel 2 interrupt pending register
//  Reserved                0xF0050058 ~ 0xF005005C
#define ASIC_GDMA_DCON3     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50060)) // GDMA channel 3 control register
#define ASIC_GDMA_DSAR3     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50064)) // GDMA channel 3 source address register
#define ASIC_GDMA_DDAR3     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50068)) // GDMA channel 3 destination address register
#define ASIC_GDMA_DTCR3     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5006C)) // GDMA channel 3 transfer count register
#define ASIC_GDMA_DRER3     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50070)) // GDMA channel 3 run enable register
#define ASIC_GDMA_DIPR3     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50074)) // GDMA channel 3 interrupt pending register
//  Reserved                0xF0050078 ~ 0xF005007C
#define ASIC_GDMA_DCON4     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50080)) // GDMA channel 4 control register
#define ASIC_GDMA_DSAR4     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50084)) // GDMA channel 4 source address register
#define ASIC_GDMA_DDAR4     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50088)) // GDMA channel 4 destination address register
#define ASIC_GDMA_DTCR4     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5008C)) // GDMA channel 4 transfer count register
#define ASIC_GDMA_DRER4     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50090)) // GDMA channel 4 run enable register
#define ASIC_GDMA_DIPR4     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x50094)) // GDMA channel 4 interrupt pending register
//  Reserved                0xF0050098 ~ 0xF005009C
#define ASIC_GDMA_DCON5     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x500A0)) // GDMA channel 5 control register
#define ASIC_GDMA_DSAR5     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x500A4)) // GDMA channel 5 source address register
#define ASIC_GDMA_DDAR5     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x500A8)) // GDMA channel 5 destination address register
#define ASIC_GDMA_DTCR5     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x500AC)) // GDMA channel 5 transfer count register
#define ASIC_GDMA_DRER5     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x500B0)) // GDMA channel 5 run enable register
#define ASIC_GDMA_DIPR5     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x500B4)) // GDMA channel 5 interrupt pending register
//  Reserved                0xF00500B8 ~ 0xF0050FFC
#define ASIC_GDMA_DPRIC     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x51000)) // GDMA priority configuration register
//  Reserved                0xF0051004 ~ 0xF0051FFC
#define ASIC_GDMA_DPRIF     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x52000)) // GDMA programmable priority register for fixed
//  Reserved                0xF0052004 ~ 0xF0052FFC
#define ASIC_GDMA_DPRIR     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x53000)) // GDMA programmable priority register for round-robin


//
// Bits in the ASIC_GDMA_DCON0 register
//
#define GDMACON0_RUN            (0x01 << 0)
#define GDMACON0_EXTDREQ        (0x01 << 1)
#define GDMACON0_BLOCK          (0x01 << 4)
#define GDMACON0_TX_HALFWORD    (0x01 << 6)
#define GDMACON0_SRC_INC        (0x00 << 8)
#define GDMACON0_SRC_FIX        (0x02 << 8)
#define GDMACON0_SRC_DIR        (0x03 << 8)
#define GDMACON0_DST_INC        (0x00 << 10)
#define GDMACON0_DST_FIX        (0x02 << 10)
#define GDMACON0_DST_DIR        (0x03 << 10)
#define GDMACON0_DMA_INT_EN     (0x01 << 12)
#define GDMACON_ACK_CYCLE_16    (0x0F << 13)
#define GDMACON0_BUSY           (0x01 << 31)

//--------------------------------------
// Console UART Special Registers
//--------------------------------------
#define ASIC_UART_CUCON     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x60000)) // Console UART control register
#define ASIC_UART_CUSTAT    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x60004)) // Console UART status register
#define ASIC_UART_CUINT     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x60008)) // Console UART interrupt enable register
#define ASIC_UART_CUTXBUF   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x6000C)) // Console UART transmit data register (Byte)
#define ASIC_UART_CURXBUF   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x60010)) // Console UART receive data register (Byte)
#define ASIC_UART_CUBRD     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x60014)) // Console UART baud rate divisor register
#define ASIC_UART_CUCHAR1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x60018)) // Console UART control character register 1
#define ASIC_UART_CUCHAR2   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x6001C)) // Console UART control character register 2

// Bits in the ASIC_UART_CUCON register
#define CUCON_TMODE_MASK    0x00000003  // CUCON[1:0] Transmit mode
#define CUCON_TMODE_DISABLE 0x00000000  // 0: Disable Tx mode
#define CUCON_TMODE_CPUREQ  0x00000001  // 1: CPU request

#define CUCON_RMODE_MASK    0x0000000C  // CUCON[3:2] Transmit mode
#define CUCON_RMODE_DISABLE 0x00000000  // 0: Disable Rx mode
#define CUCON_RMODE_CPUREQ  0x00000004  // 1: CPU request

#define CUCON_SBR_ON        0x00000010  // CUCON[4] Set this bit to one to cause the Console UART to send a break.
#define CUCON_SCSEL_EXTUCLK 0x00000020  // CUCON[5] Clock Source: 0 = Internal (PCLK2), 1 = External (EXT_UCLK)
#define CUCON_LOOPB_ON      0x00000080  // CUCON[7] Enable loop-back mode

#define CUCON_PMD_MASK      0x00000700  // CUCON[10:8] Parity mode
#define CUCON_PMD_NONE      0x00000000  // 0xx = No parity.
#define CUCON_PMD_ODD       0x00000400  // 100 = Odd parity.
#define CUCON_PMD_EVEN      0x00000500  // 101 = Even parity.
#define CUCON_PMD_FORCE1    0x00000600  // 110 = Parity forced/checked as 1
#define CUCON_PMD_FORCE0    0x00000700  // 111 = Parity forced/checked as 0

#define CUCON_STB_MASK      0x00000800  // CUCON[11] Number of Stop bits
#define CUCON_STB_ONE       0x00000000  // 0 = One stop bit per frame
#define CUCON_STB_TWO       0x00000800  // 1 = Two stop bit per frame

#define CUCON_WL_MASK       0x00003000  // CUCON[13:12] Number of data bits to be transmitted
#define CUCON_WL_5BIT       0x00000000  // 00 = 5bits
#define CUCON_WL_6BIT       0x00001000  // 01 = 6bits
#define CUCON_WL_7BIT       0x00002000  // 10 = 7bits
#define CUCON_WL_8BIT       0x00003000  // 11 = 8bits