device.h

source code of armboot for s3c4510

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    device.h
 *
 * Purpose:
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 */


#ifndef __DEVICE_H__
#define __DEVICE_H__




/*---------------------  Export Definitions  ------------------------*/

/*************************************************************************/
/* Format of the Program Status Register                                 */
/*************************************************************************/
/*                                                                       */
/* 31  30  29   28         7   6   5   4   3   2   1   0                 */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
/*| N | Z | C | V |      | I | F | T |     M4 ~ M0       |               */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
/*                                                                       */
/* Processor Mode and Mask                                               */
/*                                                                       */
/*************************************************************************/

#define I_Bit           0x80            //IRQ disable
#define F_Bit           0x40            //FIQ disable
#define T_Bit           0x20            //Thumb state, read only
#define IFRQ_DISABLE    0xC0            //Interrupt disable mask value
#define IFRQ_ENABLE     0x00            //Interrupt enable mask value
#define IFRQ_MASK       0xC0            //Interrupt lockout mask value

#ifndef UND_MODE
#define UND_MODE        0x1B            //(UND) Undefine Mode
#endif
#define ABT_MODE        0x17            //(ABT) Abort Mode
#define SVC_MODE        0x13            //(SVC) Supervisor Mode
#define IRQ_MODE        0x12            //(IRQ) Interrupt Mode
#define FIQ_MODE        0x11            //(FIQ) Fast Interrupt Mode
#define USR_MODE        0x10            //(USR) User Mode
#define SYS_MODE        0x1F            //(SYS) System Mode
#ifndef MODE_MASK
#define MODE_MASK       0x1F            //Processor Mode Mask
#endif


//--------------------------------------
// Memory area layout definition
//--------------------------------------
#define ASIC_DRAM_BASE_ADDR         0x00000000
#define ASIC_LOADER_RUN_BASE_ADDR   0x00020000
#define ASIC_VEC_TBL_BASE_ADDR      0x00F00000  // limit addr of exception vector table
#define ASIC_DRAM_SIZE              0x01000000  // size == 8MB x 2 == 16MB

#define ASIC_ROM_BASE_ADDR          0x80000000  // it is the actual ROM base address after remap
#define ASIC_ROM_0_SIZE             0x00400000  // size == 4MB
#define ASIC_ROM_1_SIZE             0x00400000  // size == 4MB
                                                // Although if when physically ROM0 is 512KB
                                                // but we still configure it as 4MB anyway

#define ASIC_EXTIO_BASE_ADDR        (0x80000000)
#if 0
#define ASIC_CPUIF_BASE_ADDR        (0x81000000)    // base addr of CPU IF; DMA_ack has issue, so cann't use.
#endif
//#define ASIC_CPUIF_BASE_ADDR        (0x81000030)    // Support one DMA channel, use A3 pin be DMA_ack.
//#define ASIC_CPUIF_BASE_ADDR        (0x03604000)    // by hill 20070920
//#define ASIC_CPUIF_BASE_ADDR         (0x07604000)	 // by hill 20070920
#define ASIC_CPUIF_BASE_ADDR         (0x07604000)	 // by hill 20070920
#define ASIC_MODULE_BASE_ADDR       (0x82000000)    // base addr of Module card; not use


//--------------------------------------
// Special Register Start Address After System Reset
//--------------------------------------
//#define ASIC_SOC_BASE_ADDR  0xF0000000
#define ASIC_SOC_BASE_ADDR  0x03ff0000		//modified by hill 20070920
#define ASIC_NON_CACHE_ADDR 0x00000000  // address offset for non-cache access
#define ASIC_DMA_MEM_BASE   0x00800000  // should conform to devicea.S
#define ASIC_DMA_MEM_SIZE   0x00800000  // should conform to devicea.S

//#define fMCLK_MHz           133000000
//#define MHz                 1000000
//#define fMCLK               (fMCLK_MHz / MHz)

//--------------------------------------
// System Configuration Special Register
//--------------------------------------
#define ASIC_SYS_SYSCFG     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0000)) // System configuration register
#define ASIC_SYS_PDCODE     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0004)) // Product code and revision number register
#define ASIC_SYS_MISCREG    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0008)) // Miscellaneous register
#define ASIC_SYS_PCLKDIS    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x000C)) // Peripheral clock disable register
#define ASIC_SYS_CLKST      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0010)) // Clock Status register
#define ASIC_SYS_HPRIF      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0014)) // AHB bus master fixed priority register
#define ASIC_SYS_HPRIR      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0018)) // AHB bus master round-robin priority register
#define ASIC_SYS_CPLLCON    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x001C)) // Core PLL Configuration Register
#define ASIC_SYS_SPLLCON    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0020)) // PCI & PC Card PLL Configuration Register
#define ASIC_SYS_UPLLCON    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0024)) // USB PLL Configuration Register
#define ASIC_SYS_PPLLCON    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0028)) // PHY PLL Configuration Register

//hill 20070921
#define ASIC_SYS_EXTACON0 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3008))
#define ASIC_SYS_EXTACON1 (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x300C))

//---------------------------------------------
// Ext. I/O Bank Controller Special Registers
//---------------------------------------------
#define ASIC_EIO_B0CON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10000)) // Bank 0 control register
#define ASIC_EIO_B1CON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10004)) // Bank 1 control register
#define ASIC_EIO_B2CON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10008)) // Bank 2 control register
#define ASIC_EIO_B3CON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x1000C)) // Bank 3 control register
#define ASIC_EIO_B4CON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10010)) // Bank 4 control register
#define ASIC_EIO_B5CON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10014)) // Bank 5 control register
#define ASIC_EIO_B6CON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10018)) // Bank 6 control register
#define ASIC_EIO_B7CON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x1001C)) // Bank 7 control register
#define ASIC_EIO_MUXBCON    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10020)) // Muxed bus control register
#define ASIC_EIO_WAITCON    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10024)) // Wait control register
#define ASIC_EIO_WDSCON     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x10028)) // Wait data setup cycle control register

//--------------------------------------
// SDRAM Special Registers
//--------------------------------------
#define ASIC_SDRAM_CFGREG   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x20000)) // Configuration register
#define ASIC_SDRAM_CMDREG   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x20004)) // Command register
#define ASIC_SDRAM_REFREG   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x20008)) // Refresh timer register
#define ASIC_SDRAM_WBTOREG  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x2000C)) // Write buffer time-out register

//--------------------------------------
// I/O Port Special Registers
//--------------------------------------
//#define ASIC_IOP_MODE1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x30000)) // I/O port mode select register for port 0 to 31
#define ASIC_IOP_MODE1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5000)) // hill 20070920
#define ASIC_IOP_MODE2      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x30004)) // I/O port mode select register for port 32 to 63
//#define ASIC_IOP_CON1       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x30008)) // I/O port function select register for port 0 to 31
#define ASIC_IOP_CON1       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5004)) //hill 20070920
#define ASIC_IOP_CON2       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3000C)) // I/O port function select register for port 32 to 63
#define ASIC_IOP_GDMA       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x30010)) // I/O port special function register for GDMA
#define ASIC_IOP_EXTINT     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x30014)) // I/O port special function register for external interrupt
#define ASIC_IOP_EXTINTPND  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x30018)) // I/O port external interrupt clear register
//#define ASIC_IOP_DATA1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3001C)) // I/O port data register for port 0 to 31
#define ASIC_IOP_DATA1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5008)) // hill 20070920
#define ASIC_IOP_DATA2      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x30020)) // I/O port data register for port 32 to 63
#define ASIC_IOP_DRV1       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x30024)) // I/O port drive control register for port 0 to 31
#define ASIC_IOP_DRV2       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x30028)) // I/O port drive control register for port 32 to 63

//--------------------------------------