pcilib.h

来自「source code of armboot for s3c4510」· C头文件 代码 · 共 187 行

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    pcilib.h
 *
 * Purpose: Diagnose PCI
 *
 * Author:  Henry Lin
 *
 * Date:    July 8, 2005
 *
 */


#ifndef __PCILIB_H__
#define __PCILIB_H__

#if !defined(__TTYPE_H__)
#include "ttype.h"
#endif




/*---------------------  Export Definitions  ------------------------*/
#define PCI_MAX_SLOT    21  //Max slot of bus 0 is 21 (IDSEL is matched by AD[11] - AD[31])

#define PCI_MAX_BAR     6

/* PCI Class Codes */
#define PCI_HISTORY_CLASS               0x00
#define PCI_STORAGE_CLASS               0x01
#define PCI_NETWORK_CLASS               0x02
#define PCI_DISPLAY_CLASS               0x03
#define PCI_MMEDIA_CLASS                0x04
#define PCI_MEMORY_CLASS                0x05
#define PCI_BRIDGE_CLASS                0x06
#define PCI_COMMS_CLASS                 0x07
#define PCI_PERIPH_CLASS                0x08
#define PCI_INPUT_CLASS                 0x09
#define PCI_DOCKING_CLASS               0x0A
#define PCI_PROCESS_CLASS               0x0B
#define PCI_SERIAL_CLASS                0x0C
#define PCI_MISC_CLASS                  0xFF

#define PCI_2PCI_SUB                    0x04

/* handy values */
#define PCI_INVALID                     0xFFFFFFFF
#define PCI_NOTFITTED                   0xFFFF

/* handy sizes */
#define SZ_1K                           0x00000400
#define SZ_4K                           0x00001000
#define SZ_8K                           0x00002000
#define SZ_16K                          0x00004000
#define SZ_64K                          0x00010000
#define SZ_128K                         0x00020000
#define SZ_256K                         0x00040000
#define SZ_512K                         0x00080000

#define SZ_1M                           0x00100000
#define SZ_2M                           0x00200000
#define SZ_4M                           0x00400000
#define SZ_8M                           0x00800000
#define SZ_16M                          0x01000000
#define SZ_30M                          0x01e00000
#define SZ_32M                          0x02000000
#define SZ_64M                          0x04000000
#define SZ_128M                         0x08000000
#define SZ_256M                         0x10000000
#define SZ_512M                         0x20000000

#define SZ_1G                           0x40000000
#define SZ_2G                           0x80000000


/*  PCI Command Register
 */
#define PCI_IO_ENABLE                   0x0001
#define PCI_MEM_ENABLE                  0x0002
#define PCI_MASTER_ENABLE               0x0004
#define PCI_MEM_WRINVALID               0x0010
#define PCI_FAST_B2B                    0x0200
#define MAX(val1, val2)         ( ((val1) > (val2)) ? val1 : val2 )

/* default alignments to use for IO and Memory space */
#define DEFAULT_MEMORY_ALIGNMENT    0x1000          //2 4 Kbytes
#define DEFAULT_IO_ALIGNMENT        0x800           //2 2 Kbytes
#define EXPROM_INSERTED             0x55aa


// PCI Command define
#define CMD_MEMORY_WRITE_AND_INVALIDATE 0xf     //0x7
#define CMD_MEMORY_READ_LINE            0xe     //0x7
#define CMD_DUAL_ADDRESS_CYCLE          0xd     //0x6
#define CMD_MEMORY_READ_MULTIPLE        0xc     //0x6
#define CMD_CONFIG_WRITE                0xb     //0x5
#define CMD_CONFIG_READ                 0xa     //0x5
#define CMD_MEMORY_WRITE                0x7     //0x3
#define CMD_MEMORY_READ                 0x6     //0x3
#define CMD_IO_WRITE                    0x3     //0x1
#define CMD_IO_READ                     0x2     //0x1
#define CMD_SPECIAL_CYCLE               0x1     //0x0
#define CMD_INT_ACK                     0x0     //0x0

/*---------------------  Export Types  ------------------------------*/
/* A PCI device, the PCI configuration code builds a list of PCI devices */
typedef struct PCIDevice {
    struct PCIDevice *next;   // next PCI device in the system (all buses)
    struct PCIDevice *sibling;    // next device on this bus
    struct PCIDevice *parent; // this device's parent device

    // Flags
    struct {
        UINT    bridge:1;  // This is a PCI-PCI bridge device
        UINT    spare:15;
    } flags;

    // This part of the structure is only relevent if this is a PCI-PCI bridge
    struct {
        struct  PCIDevice *children;     // pointer to child devices of this PCI-PCI bridge
        UINT8   number;       // This bus's number
        UINT8   primary;      // number of primary bridge
        UINT8   secondary;    // number of secondary bridge
        UINT8   subordinate;  // number of subordinate buses
    } bridge;

    // Vendor/Device is a unique key across all PCI devices.
    UINT16  vendor;
    UINT16  device;

    // PCI Configuration space addressing information for this device
    UINT8   bus;
    UINT8   slot;
    UINT8   func;
} PCIDevice_t;

/*---------------------  Export Macros  -----------------------------*/

/*---------------------  Export Classes  ----------------------------*/

/*---------------------  Export Variables  --------------------------*/

/*---------------------  Export Functions  --------------------------*/
void PCILIB_Scan(UINT32* pu32IoBA, UINT32* pu32MemBA);

void PCILIB_Init(void);
UINT8 PCILIB_ScanPCI(PCIDevice_t * bus);

void PCIir_ConfigurePCIDevices (PCIDevice_t * bus);
PCIDevice_t * PCIir_AllocatePCIDevice (void);
PCIDevice_t * PCIr_AddPCIDevice (PCIDevice_t * bridge, UINT32 bus, UINT32 slot, UINT32 func,
           UINT16 vendor, UINT16 device);

void PCIir_AssignResources (PCIDevice_t * device);
void PCIir_AllocateInterrupt (PCIDevice_t * device);

UINT8 PCIMapInterrupt(UINT8 pin, UINT8 slot);
void PCI_Action (UINT32 bus, UINT32 slot,UINT32 func);
void PCIr_ForEveryDevice (void (action) (UINT32, UINT32, UINT32));

UINT32 ALIGN(UINT32 val, UINT32 align);
UINT8 bridgeSwizzle(UINT8 pin, UINT32 slot);




#endif