mcucpld.map.qmsg

51单片机开发与应用技术详解(珍藏版)PPT及源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 13 10:01:29 2006 " "Info: Processing started: Wed Dec 13 10:01:29 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off MCUCPLD -c MCUCPLD " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off MCUCPLD -c MCUCPLD" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MCUCPLD.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file MCUCPLD.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MCUCPLD-Arch " "Info: Found design unit 1: MCUCPLD-Arch" {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 MCUCPLD " "Info: Found entity 1: MCUCPLD" {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SA MCUCPLD.vhd(32) " "Warning: VHDL Process Statement warning at MCUCPLD.vhd(32): signal \"SA\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SB MCUCPLD.vhd(33) " "Warning: VHDL Process Statement warning at MCUCPLD.vhd(33): signal \"SB\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SC MCUCPLD.vhd(34) " "Warning: VHDL Process Statement warning at MCUCPLD.vhd(34): signal \"SC\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SD MCUCPLD.vhd(35) " "Warning: VHDL Process Statement warning at MCUCPLD.vhd(35): signal \"SD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "SA MCUCPLD.vhd(21) " "Warning: VHDL Process Statement warning at MCUCPLD.vhd(21): signal or variable \"SA\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"SA\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "SB MCUCPLD.vhd(21) " "Warning: VHDL Process Statement warning at MCUCPLD.vhd(21): signal or variable \"SB\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"SB\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "SC MCUCPLD.vhd(21) " "Warning: VHDL Process Statement warning at MCUCPLD.vhd(21): signal or variable \"SC\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"SC\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "SD MCUCPLD.vhd(21) " "Warning: VHDL Process Statement warning at MCUCPLD.vhd(21): signal or variable \"SD\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"SD\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "MCUCPLD.vhd" "" { Text "F:/ZJL/WriteMCU/第20章单片机与CPLD接口/MCUCPLD/MCUCPLD.vhd" 21 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "74 " "Info: Implemented 74 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "32 " "Info: Implemented 32 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 13 10:01:33 2006 " "Info: Processing ended: Wed Dec 13 10:01:33 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}