counter.tan.qmsg

8位计数器

{ "Info" "ITDB_FULL_TCO_RESULT" "clk2 y\[0\] lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 17.300 ns register " "Info: tco from clock clk2 to destination pin y\[0\] through register lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] is 17.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 5.300 ns + Longest register " "Info: + Longest clock path from clock clk2 to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk2 1 CLK Pin_42 17 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 17; CLK Node = 'clk2'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "" { clk2 } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC8_B7 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_B7; Fanout = 4; REG Node = 'lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "2.500 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.900 ns + Longest register pin " "Info: + Longest register to pin delay is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 1 REG LC8_B7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B7; Fanout = 4; REG Node = 'lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.800 ns) 4.800 ns y\[0\]~0 2 COMB LC1_B20 1 " "Info: 2: + IC(3.000 ns) + CELL(1.800 ns) = 4.800 ns; Loc. = LC1_B20; Fanout = 1; COMB Node = 'y\[0\]~0'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "4.800 ns" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] y[0]~0 } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.100 ns) 10.900 ns y\[0\] 3 PIN Pin_52 0 " "Info: 3: + IC(1.000 ns) + CELL(5.100 ns) = 10.900 ns; Loc. = Pin_52; Fanout = 0; PIN Node = 'y\[0\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "6.100 ns" { y[0]~0 y[0] } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns 63.30 % " "Info: Total cell delay = 6.900 ns ( 63.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 36.70 % " "Info: Total interconnect delay = 4.000 ns ( 36.70 % )" {  } {  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "10.900 ns" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] y[0]~0 y[0] } "NODE_NAME" } } }  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "10.900 ns" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] y[0]~0 y[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk2 y\[6\] lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 16.800 ns register " "Info: Minimum tco from clock clk2 to destination pin y\[6\] through register lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] is 16.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 5.300 ns + Shortest register " "Info: + Shortest clock path from clock clk2 to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk2 1 CLK Pin_42 17 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 17; CLK Node = 'clk2'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "" { clk2 } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC2_B7 7 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B7; Fanout = 7; REG Node = 'lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "2.500 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.400 ns + Shortest register pin " "Info: + Shortest register to pin delay is 10.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 1 REG LC2_B7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B7; Fanout = 7; REG Node = 'lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.800 ns) 4.300 ns y\[6\]~6 2 COMB LC4_B12 1 " "Info: 2: + IC(2.500 ns) + CELL(1.800 ns) = 4.300 ns; Loc. = LC4_B12; Fanout = 1; COMB Node = 'y\[6\]~6'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "4.300 ns" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] y[6]~6 } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.100 ns) 10.400 ns y\[6\] 3 PIN Pin_39 0 " "Info: 3: + IC(1.000 ns) + CELL(5.100 ns) = 10.400 ns; Loc. = Pin_39; Fanout = 0; PIN Node = 'y\[6\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "6.100 ns" { y[6]~6 y[6] } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns 66.35 % " "Info: Total cell delay = 6.900 ns ( 66.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns 33.65 % " "Info: Total interconnect delay = 3.500 ns ( 33.65 % )" {  } {  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "10.400 ns" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] y[6]~6 y[6] } "NODE_NAME" } } }  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "10.400 ns" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] y[6]~6 y[6] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 01 15:38:04 2007 " "Info: Processing ended: Thu Nov 01 15:38:04 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}