counter.tan.qmsg

8位计数器

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk2 " "Info: Assuming node clk2 is an undefined clock" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 5 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node clk1 is an undefined clock" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 5 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk2 register lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] register i~4 72.46 MHz 13.8 ns Internal " "Info: Clock clk2 has Internal fmax of 72.46 MHz between source register lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] and destination register i~4 (period= 13.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.200 ns + Longest register register " "Info: + Longest register to register delay is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_B7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B7; Fanout = 7; REG Node = 'lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.200 ns) 3.700 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC1_B8 2 " "Info: 2: + IC(2.500 ns) + CELL(1.200 ns) = 3.700 ns; Loc. = LC1_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "3.700 ns" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.000 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC2_B8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 4.000 ns; Loc. = LC2_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "0.300 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.300 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC3_B8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.300 ns; Loc. = LC3_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "0.300 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.600 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC4_B8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.600 ns; Loc. = LC4_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "0.300 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.900 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC5_B8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.900 ns; Loc. = LC5_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "0.300 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.200 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC6_B8 2 " "Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 5.200 ns; Loc. = LC6_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "0.300 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.500 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 8 COMB LC7_B8 1 " "Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 5.500 ns; Loc. = LC7_B8; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "0.300 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 6.800 ns lpm_add_sub:i_rtl_1\|addcore:adder\|unreg_res_node\[7\] 9 COMB LC8_B8 2 " "Info: 9: + IC(0.000 ns) + CELL(1.300 ns) = 6.800 ns; Loc. = LC8_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|unreg_res_node\[7\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "1.300 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/addcore.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 10.200 ns i~4 10 REG LC4_B9 1 " "Info: 10: + IC(2.200 ns) + CELL(1.200 ns) = 10.200 ns; Loc. = LC4_B9; Fanout = 1; REG Node = 'i~4'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "3.400 ns" { lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7] i~4 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 53.92 % " "Info: Total cell delay = 5.500 ns ( 53.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 46.08 % " "Info: Total interconnect delay = 4.700 ns ( 46.08 % )" {  } {  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "10.200 ns" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7] i~4 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock clk2 to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk2 1 CLK Pin_42 17 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 17; CLK Node = 'clk2'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "" { clk2 } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns i~4 2 REG LC4_B9 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B9; Fanout = 1; REG Node = 'i~4'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "2.500 ns" { clk2 i~4 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 i~4 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 5.300 ns - Longest register " "Info: - Longest clock path from clock clk2 to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk2 1 CLK Pin_42 17 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 17; CLK Node = 'clk2'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "" { clk2 } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" "" "" { Text "e:/Documents and Settings/user/My Documents/pxh/2/counter.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_B7 7 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B7; Fanout = 7; REG Node = 'lpm_counter:q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "2.500 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } }  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 i~4 } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } {  } 0}  } { { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "10.200 ns" { lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7] i~4 } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 i~4 } "NODE_NAME" } } } { "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" "" "" { Report "e:/Documents and Settings/user/My Documents/pxh/2/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "e:/Documents and Settings/user/My Documents/pxh/2/db/counter.quartus_db" { Floorplan "" "" "5.300 ns" { clk2 lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk1 " "Info: No valid register-to-register paths exist for clock clk1" {  } {  } 0}