counter.tan.rpt

8位计数器

+----------------------------------------------------------------------------------------------------------------------------------+
; Minimum tco                                                                                                                      ;
+-----------------------------------------------------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From                                                     ; To   ; From Clock ;
+---------------+------------------+----------------+----------------------------------------------------------+------+------------+
; N/A           ; None             ; 16.800 ns      ; lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; y[6] ; clk2       ;
; N/A           ; None             ; 16.800 ns      ; lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; y[7] ; clk2       ;
; N/A           ; None             ; 17.100 ns      ; lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; y[1] ; clk2       ;
; N/A           ; None             ; 17.100 ns      ; lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; y[2] ; clk2       ;
; N/A           ; None             ; 17.100 ns      ; lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; y[3] ; clk2       ;
; N/A           ; None             ; 17.100 ns      ; lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; y[4] ; clk2       ;
; N/A           ; None             ; 17.100 ns      ; lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; y[5] ; clk2       ;
; N/A           ; None             ; 17.300 ns      ; lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; y[0] ; clk2       ;
+---------------+------------------+----------------+----------------------------------------------------------+------+------------+


+---------------------------+
; Timing Analyzer Messages  ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Thu Nov 01 15:38:04 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off counter -c counter
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk2 is an undefined clock
    Info: Assuming node clk1 is an undefined clock
Info: Clock clk2 has Internal fmax of 72.46 MHz between source register lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] and destination register i~4 (period= 13.8 ns)
    Info: + Longest register to register delay is 10.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B7; Fanout = 7; REG Node = 'lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: 2: + IC(2.500 ns) + CELL(1.200 ns) = 3.700 ns; Loc. = LC1_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0]'
        Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 4.000 ns; Loc. = LC2_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1]'
        Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.300 ns; Loc. = LC3_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2]'
        Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.600 ns; Loc. = LC4_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.900 ns; Loc. = LC5_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 5.200 ns; Loc. = LC6_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 5.500 ns; Loc. = LC7_B8; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6]'
        Info: 9: + IC(0.000 ns) + CELL(1.300 ns) = 6.800 ns; Loc. = LC8_B8; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7]'
        Info: 10: + IC(2.200 ns) + CELL(1.200 ns) = 10.200 ns; Loc. = LC4_B9; Fanout = 1; REG Node = 'i~4'
        Info: Total cell delay = 5.500 ns ( 53.92 % )
        Info: Total interconnect delay = 4.700 ns ( 46.08 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock clk2 to destination register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 17; CLK Node = 'clk2'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B9; Fanout = 1; REG Node = 'i~4'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: - Longest clock path from clock clk2 to source register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 17; CLK Node = 'clk2'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B7; Fanout = 7; REG Node = 'lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: No valid register-to-register paths exist for clock clk1
Info: tco from clock clk2 to destination pin y[0] through register lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] is 17.300 ns
    Info: + Longest clock path from clock clk2 to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 17; CLK Node = 'clk2'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_B7; Fanout = 4; REG Node = 'lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 10.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B7; Fanout = 4; REG Node = 'lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7]'
        Info: 2: + IC(3.000 ns) + CELL(1.800 ns) = 4.800 ns; Loc. = LC1_B20; Fanout = 1; COMB Node = 'y[0]~0'
        Info: 3: + IC(1.000 ns) + CELL(5.100 ns) = 10.900 ns; Loc. = Pin_52; Fanout = 0; PIN Node = 'y[0]'
        Info: Total cell delay = 6.900 ns ( 63.30 % )
        Info: Total interconnect delay = 4.000 ns ( 36.70 % )
Info: Minimum tco from clock clk2 to destination pin y[6] through register lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] is 16.800 ns
    Info: + Shortest clock path from clock clk2 to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 17; CLK Node = 'clk2'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B7; Fanout = 7; REG Node = 'lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Shortest register to pin delay is 10.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B7; Fanout = 7; REG Node = 'lpm_counter:q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
        Info: 2: + IC(2.500 ns) + CELL(1.800 ns) = 4.300 ns; Loc. = LC4_B12; Fanout = 1; COMB Node = 'y[6]~6'
        Info: 3: + IC(1.000 ns) + CELL(5.100 ns) = 10.400 ns; Loc. = Pin_39; Fanout = 0; PIN Node = 'y[6]'
        Info: Total cell delay = 6.900 ns ( 66.35 % )
        Info: Total interconnect delay = 3.500 ns ( 33.65 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Nov 01 15:38:04 2007
    Info: Elapsed time: 00:00:00