📄 cstartup_sam7.lst
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ARM COMPILER V2.42, Cstartup_SAM7 14/02/07 10:22:56 PAGE 1
ARM COMPILER V2.42, COMPILATION OF MODULE Cstartup_SAM7
OBJECT MODULE PLACED IN Cstartup_SAM7.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe Cstartup_SAM7.c THUMB BROWSE DEBUG TABS(4)
stmt level source
1 // ----------------------------------------------------------------------------
2 // ATMEL Microcontroller Software Support - ROUSSET -
3 // ----------------------------------------------------------------------------
4 // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
5 // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
7 // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
8 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
9 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
10 // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
11 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
12 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
13 // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
14 // ----------------------------------------------------------------------------
15 // File Name : Cstartup_SAM7.c
16 // Object : Low level initialisations written in C for IAR Tools
17 // Creation : FBr 01-Sep-2005
18 // 1.0 08-Sep-2005 JPP : Suppress Reset
19 // ----------------------------------------------------------------------------
20
21 #include "project.h"
22
23 // The following functions must be write in ARM mode this function called directly by exception vector
24 extern void AT91F_Spurious_handler(void);
25 extern void AT91F_Default_IRQ_handler(void);
26 extern void AT91F_Default_FIQ_handler(void);
27
28 //*----------------------------------------------------------------------------
29 //* \fn AT91F_LowLevelInit
30 //* \brief This function performs very low level HW initialization
31 //* this function can use a Stack, depending the compilation
32 //* optimization mode
33 //*----------------------------------------------------------------------------
34 void AT91F_LowLevelInit(void)
35 {
36 1 unsigned char i;
37 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
38 1 // EFC Init
39 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
40 1 AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS; // 1 Wait State necessary to work at 48MHz
41 1
42 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
43 1 // Init PMC Step 1. Enable Main Oscillator
44 1 // Main Oscillator startup time is board specific:
45 1 // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms (0x40 for AT91C_CKGR_OSCOUNT fi
-eld)
46 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
47 1 AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
48 1 // Wait Main Oscillator stabilization
49 1 while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
50 1
51 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
52 1 // Init PMC Step 2.
53 1 // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz
54 1 // PLL Startup time depends on PLL RC filter: worst case is choosen
55 1 // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus Specification (+/- 0.25% for full
- speed)
56 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
57 1 AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 | AT91C_CKGR_OUT_0 | AT91C_CKGR_PLLCOUNT |
ARM COMPILER V2.42, Cstartup_SAM7 14/02/07 10:22:56 PAGE 2
58 1 (AT91C_CKGR_MUL & (72 << 16)) | (AT91C_CKGR_DIV & 14);
59 1 // Wait for PLL stabilization
60 1 while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
61 1 // Wait until the master clock is established for the case we already turn on the PLL
62 1 while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
63 1
64 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
65 1 // Init PMC Step 3.
66 1 // Selection of Master Clock MCK (equal to Processor Clock PCK) equal to PLL/2 = 48MHz
67 1 // The PMC_MCKR register must not be programmed in a single write operation (see. Product Errata Shee
-t)
68 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
69 1 AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
70 1 // Wait until the master clock is established
71 1 while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
72 1
73 1 AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
74 1 // Wait until the master clock is established
75 1 while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
76 1
77 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
78 1 // Disable Watchdog (write once register)
79 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
80 1 AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
81 1
82 1 ////////////////////////////////////////////////////////////////////////////////////////////////////
83 1 // Init AIC: assign corresponding handler for each interrupt source
84 1 /////////////////////////////////////////////////////////////////////////////////////////////////////
85 1 AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
86 1 for (i = 1; i < 31; i++) {
87 2 AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
88 2 }
89 1 AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
90 1 }
ARM COMPILER V2.42, Cstartup_SAM7 14/02/07 10:22:56 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN CODE16 (AT91F_Spurious_handler?T)
EXTERN CODE16 (AT91F_Default_IRQ_handler?T)
EXTERN CODE16 (AT91F_Default_FIQ_handler?T)
EXTERN CODE16 (?C?UDIV?T)
*** PUBLICS:
PUBLIC AT91F_LowLevelInit?T
*** CODE SEGMENT '?PR?AT91F_AIC_ConfigureIt?T?Cstartup_SAM7':
53: __inline unsigned int AT91F_AIC_ConfigureIt (
00000000 B4F0 PUSH {R4-R7}
00000002 ---- Variable 'src_type' assigned to Register 'R3' ----
00000002 1C17 MOV R7,R2 ; priority
00000004 ---- Variable 'priority' assigned to Register 'R7' ----
00000004 1C0E MOV R6,R1 ; irq_id
00000006 ---- Variable 'irq_id' assigned to Register 'R6' ----
00000006 1C04 MOV R4,R0 ; pAic
00000008 ---- Variable 'pAic' assigned to Register 'R4' ----
00000008 B081 SUB R13,#0x4
59: {
0000000A ; SCOPE-START
63: oldHandler = pAic->AIC_SVR[irq_id];
0000000A 1C31 MOV R1,R6 ; irq_id
0000000C 0089 LSL R1,R1,#0x2 ; irq_id
0000000E 1C20 MOV R0,R4 ; pAic
00000010 1840 ADD R0,R1 ; pAic
00000012 3080 ADD R0,#0x80
00000014 6800 LDR R0,[R0,#0x0]
00000016 9000 STR R0,[R13,#0x0] ; oldHandler
65: mask = 0x1 << irq_id ;
00000018 1C30 MOV R0,R6 ; irq_id
0000001A 2501 MOV R5,#0x1
0000001C 4085 LSL R5,R0
0000001E ---- Variable 'mask' assigned to Register 'R5' ----
67: pAic->AIC_IDCR = mask ;
0000001E 1C29 MOV R1,R5 ; mask
00000020 4A49 LDR R2,=0x124
00000022 1C20 MOV R0,R4 ; pAic
00000024 5081 STR R1,[R0,R2]
69: pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
00000026 9A01 LDR R2,[R13,#0x4] ; newHandler
00000028 1C31 MOV R1,R6 ; irq_id
0000002A 0089 LSL R1,R1,#0x2 ; irq_id
0000002C 1C20 MOV R0,R4 ; pAic
0000002E 1840 ADD R0,R1 ; pAic
00000030 3080 ADD R0,#0x80
00000032 6002 STR R2,[R0,#0x0]
71: pAic->AIC_SMR[irq_id] = src_type | priority ;
00000034 1C38 MOV R0,R7 ; priority
00000036 1C1A MOV R2,R3 ; src_type
00000038 4302 ORR R2,R0 ; priority
0000003A 1C31 MOV R1,R6 ; irq_id
0000003C 0089 LSL R1,R1,#0x2 ; irq_id
0000003E 1C20 MOV R0,R4 ; pAic
00000040 5042 STR R2,[R0,R1]
73: pAic->AIC_ICCR = mask ;
00000042 1C29 MOV R1,R5 ; mask
00000044 4A4A LDR R2,=0x128
00000046 1C20 MOV R0,R4 ; pAic
00000048 5081 STR R1,[R0,R2]
75: return oldHandler;
0000004A 9800 LDR R0,[R13,#0x0] ; oldHandler
ARM COMPILER V2.42, Cstartup_SAM7 14/02/07 10:22:56 PAGE 4
0000004C ; SCOPE-END
76: }
0000004C B001 ADD R13,#0x4
0000004E BCF0 POP {R4-R7}
00000050 4770 BX R14
00000052 ENDP ; 'AT91F_AIC_ConfigureIt?T'
*** CODE SEGMENT '?PR?AT91F_AIC_DisableIt?T?Cstartup_SAM7':
94: __inline void AT91F_AIC_DisableIt (
00000000 B410 PUSH {R4}
00000002 ---- Variable 'irq_id' assigned to Register 'R1' ----
00000002 1C03 MOV R3,R0 ; pAic
00000004 ---- Variable 'pAic' assigned to Register 'R3' ----
97: {
00000004 ; SCOPE-START
98: unsigned int mask = 0x1 << irq_id;
00000004 1C08 MOV R0,R1 ; irq_id
00000006 2401 MOV R4,#0x1
00000008 4084 LSL R4,R0
0000000A ---- Variable 'mask' assigned to Register 'R4' ----
100: pAic->AIC_IDCR = mask ;
0000000A 1C21 MOV R1,R4 ; mask
0000000C 4A49 LDR R2,=0x124
0000000E 1C18 MOV R0,R3 ; pAic
00000010 5081 STR R1,[R0,R2]
102: pAic->AIC_ICCR = mask ;
00000012 1C21 MOV R1,R4 ; mask
00000014 4A4A LDR R2,=0x128
00000016 1C18 MOV R0,R3 ; pAic
00000018 5081 STR R1,[R0,R2]
0000001A ; SCOPE-END
103: }
0000001A BC10 POP {R4}
0000001C 4770 BX R14
0000001E ENDP ; 'AT91F_AIC_DisableIt?T'
*** CODE SEGMENT '?PR?AT91F_AIC_SetExceptionVector?T?Cstartup_SAM7':
131: __inline unsigned int AT91F_AIC_SetExceptionVector (
00000000 B410 PUSH {R4}
00000002 1C0C MOV R4,R1 ; Handler
00000004 ---- Variable 'Handler' assigned to Register 'R4' ----
00000004 1C03 MOV R3,R0 ; pVector
00000006 ---- Variable 'pVector' assigned to Register 'R3' ----
134: {
00000006 ; SCOPE-START
135: unsigned int oldVector = *pVector;
00000006 1C18 MOV R0,R3 ; pVector
00000008 6802 LDR R2,[R0,#0x0] ; pVector
0000000A ---- Variable 'oldVector' assigned to Register 'R2' ----
137: if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
0000000A 1C20 MOV R0,R4 ; Handler
0000000C 4800 LDR R1,=0xE51FFF20
0000000E 4288 CMP R0,R1
00000010 D102 BNE L_2 ; T=0x00000018
138: *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
00000012 1C18 MOV R0,R3 ; pVector
00000014 6001 STR R1,[R0,#0x0] ; pVector
00000016 E00A B L_3 ; T=0x0000002E
00000018 L_2:
140: *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
00000018 1C18 MOV R0,R3 ; pVector
0000001A 1C21 MOV R1,R4 ; Handler
0000001C 1A09 SUB R1,R0
0000001E 3908 SUB R1,#0x8
00000020 0889 LSR R1,R1,#0x2
00000022 4800 LDR R0,=0xFF000000
00000024 4381 BIC R1,R0
00000026 4800 LDR R0,=0xEA000000
ARM COMPILER V2.42, Cstartup_SAM7 14/02/07 10:22:56 PAGE 5
00000028 4301 ORR R1,R0
0000002A 1C18 MOV R0,R3 ; pVector
0000002C 6001 STR R1,[R0,#0x0] ; pVector
0000002E L_3:
142: return oldVector;
0000002E 1C10 MOV R0,R2 ; oldVector
00000030 ; SCOPE-END
143: }
00000030 BC10 POP {R4}
00000032 4770 BX R14
00000034 ENDP ; 'AT91F_AIC_SetExceptionVector?T'
*** CODE SEGMENT '?PR?AT91F_PDC_SetNextRx?T?Cstartup_SAM7':
213: __inline void AT91F_PDC_SetNextRx (
00000000 B410 PUSH {R4}
00000002 ---- Variable 'bytes' assigned to Register 'R2' ----
00000002 1C0C MOV R4,R1 ; address
00000004 ---- Variable 'address' assigned to Register 'R4' ----
00000004 1C03 MOV R3,R0 ; pPDC
00000006 ---- Variable 'pPDC' assigned to Register 'R3' ----
218: pPDC->PDC_RNPR = (unsigned int) address;
00000006 1C21 MOV R1,R4 ; address
00000008 1C18 MOV R0,R3 ; pPDC
0000000A 6101 STR R1,[R0,#0x10]
219: pPDC->PDC_RNCR = bytes;
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