st7fmc2n6.h

该程序是ST7MC驱动三洋压缩机（交流）

#define MPHST_OO2_OR	(1 << MPHST_OO2)
#define MPHST_OO3	3		/* Output Channel 3 On/Off bit */
#define MPHST_OO3_OR	(1 << MPHST_OO3)
#define MPHST_OO4	4		/* Output Channel 4 On/Off bit */
#define MPHST_OO4_OR	(1 << MPHST_OO4)
#define MPHST_OO5	5		/* Output Channel 5 On/Off bit */
#define MPHST_OO5_OR	(1 << MPHST_OO5)
#define MPHST_IS0	6		/* Input Selection bits */
#define MPHST_IS0_OR	(1 << MPHST_IS0)
#define MPHST_IS1	7		/* Input Selection bits */
#define MPHST_IS1_OR	(1 << MPHST_IS1)
#define MPHST_IS_OR	((1 << MPHST_IS0)|(1 << MPHST_IS1))

/* D event Filter Register */
STVD7_EXTERN volatile unsigned char MDFR @0x5e;
#define MDFR_DWF0	0		/* D Window Filter bits */
#define MDFR_DWF0_OR	(1 << MDFR_DWF0)
#define MDFR_DWF1	1		/* D Window Filter bits */
#define MDFR_DWF1_OR	(1 << MDFR_DWF1)
#define MDFR_DWF2	2		/* D Window Filter bits */
#define MDFR_DWF2_OR	(1 << MDFR_DWF2)
#define MDFR_DWF3	3		/* D Window Filter bits */
#define MDFR_DWF3_OR	(1 << MDFR_DWF3)
#define MDFR_DWF_OR	((1 << MDFR_DWF0)|(1 << MDFR_DWF1)\
		|(1 << MDFR_DWF2)|(1 << MDFR_DWF3))
#define MDFR_DEF0	4		/* D Event Filter bits */
#define MDFR_DEF0_OR	(1 << MDFR_DEF0)
#define MDFR_DEF1	5		/* D Event Filter bits */
#define MDFR_DEF1_OR	(1 << MDFR_DEF1)
#define MDFR_DEF2	6		/* D Event Filter bits */
#define MDFR_DEF2_OR	(1 << MDFR_DEF2)
#define MDFR_DEF3	7		/* D Event Filter bits */
#define MDFR_DEF3_OR	(1 << MDFR_DEF3)
#define MDFR_DEF_OR	((1 << MDFR_DEF0)|(1 << MDFR_DEF1)\
		|(1 << MDFR_DEF2)|(1 << MDFR_DEF3))

/* Current feedback Filter Register */
STVD7_EXTERN volatile unsigned char MCFR @0x5f;
#define MCFR_CFW0	0		/* Current Window Filter bits */
#define MCFR_CFW0_OR	(1 << MCFR_CFW0)
#define MCFR_CFW1	1		/* Current Window Filter bits */
#define MCFR_CFW1_OR	(1 << MCFR_CFW1)
#define MCFR_CFW2	2		/* Current Window Filter bits */
#define MCFR_CFW2_OR	(1 << MCFR_CFW2)
#define MCFR_CFW_OR	((1 << MCFR_CFW0)|(1 << MCFR_CFW1)\
		|(1 << MCFR_CFW2))
#define MCFR_CFF0	3		/* Current Feedback Filter bits */
#define MCFR_CFF0_OR	(1 << MCFR_CFF0)
#define MCFR_CFF1	4		/* Current Feedback Filter bits */
#define MCFR_CFF1_OR	(1 << MCFR_CFF1)
#define MCFR_CFF2	5		/* Current Feedback Filter bits */
#define MCFR_CFF2_OR	(1 << MCFR_CFF2)
#define MCFR_CFF_OR	((1 << MCFR_CFF0)|(1 << MCFR_CFF1)\
		|(1 << MCFR_CFF2))
#define MCFR_RST	6		/* Reset MTC registers */
#define MCFR_RST_OR	(1 << MCFR_RST)
#define MCFR_RPGS	7		/* Register Page Selection */
#define MCFR_RPGS_OR	(1 << MCFR_RPGS)

/* Reference Register */
STVD7_EXTERN volatile unsigned char MREF @0x60;
#define MREF_HFRQ0	0		/* Chopper frequency selection */
#define MREF_HFRQ0_OR	(1 << MREF_HFRQ0)
#define MREF_HFRQ1	1		/* Chopper frequency selection */
#define MREF_HFRQ1_OR	(1 << MREF_HFRQ1)
#define MREF_HFRQ2	2		/* Chopper frequency selection */
#define MREF_HFRQ2_OR	(1 << MREF_HFRQ2)
#define MREF_HFRQ_OR	((1 << MREF_HFRQ0)|(1 << MREF_HFRQ1)\
		|(1 << MREF_HFRQ2))
#define MREF_HFE0	3		/* Chopping mode selection */
#define MREF_HFE0_OR	(1 << MREF_HFE0)
#define MREF_HFE1	4		/* Chopping mode selection */
#define MREF_HFE1_OR	(1 << MREF_HFE1)
#define MREF_HFE_OR	((1 << MREF_HFE0)|(1 << MREF_HFE1))
#define MREF_CFAV	5		/* Current Feedback Amplifier entry Validation */
#define MREF_CFAV_OR	(1 << MREF_CFAV)
#define MREF_CL	6		/* Current Loop Comparator Value */
#define MREF_CL_OR	(1 << MREF_CL)
#define MREF_HST	7		/* Hysteresis Comparator Value */
#define MREF_HST_OR	(1 << MREF_HST)

/* PWM Control Register */
STVD7_EXTERN volatile unsigned char MPCR @0x61;
#define MPCR_PCP0	0		/* PWM counter prescaler value */
#define MPCR_PCP0_OR	(1 << MPCR_PCP0)
#define MPCR_PCP1	1		/* PWM counter prescaler value */
#define MPCR_PCP1_OR	(1 << MPCR_PCP1)
#define MPCR_PCP2	2		/* PWM counter prescaler value */
#define MPCR_PCP2_OR	(1 << MPCR_PCP2)
#define MPCR_PCP_OR	((1 << MPCR_PCP0)|(1 << MPCR_PCP1)\
		|(1 << MPCR_PCP2))
#define MPCR_CMS	3		/* PWM Counter Mode Selection */
#define MPCR_CMS_OR	(1 << MPCR_CMS)
#define MPCR_OVFW	4		/* Phase W 100% duty cycle Selection */
#define MPCR_OVFW_OR	(1 << MPCR_OVFW)
#define MPCR_OVFV	5		/* Phase V 100% duty cycle Selection */
#define MPCR_OVFV_OR	(1 << MPCR_OVFV)
#define MPCR_OVFU	6		/* Phase U 100% duty cycle Selection */
#define MPCR_OVFU_OR	(1 << MPCR_OVFU)
#define MPCR_PMS	7		/* PWM Mode Selection */
#define MPCR_PMS_OR	(1 << MPCR_PMS)

/* Repetition Counter Register */
STVD7_EXTERN volatile unsigned char MREP @0x62;

/* Compare Phase W Preload Register High */
STVD7_EXTERN volatile unsigned char MCPWH @0x63;

/* Compare Phase W Preload Register Low */
STVD7_EXTERN volatile unsigned char MCPWL @0x64;
#define MCPWL_CPWL3	3		/* Low bits of phase W preload value */
#define MCPWL_CPWL3_OR	(1 << MCPWL_CPWL3)
#define MCPWL_CPWL4	4		/* Low bits of phase W preload value */
#define MCPWL_CPWL4_OR	(1 << MCPWL_CPWL4)
#define MCPWL_CPWL5	5		/* Low bits of phase W preload value */
#define MCPWL_CPWL5_OR	(1 << MCPWL_CPWL5)
#define MCPWL_CPWL6	6		/* Low bits of phase W preload value */
#define MCPWL_CPWL6_OR	(1 << MCPWL_CPWL6)
#define MCPWL_CPWL7	7		/* Low bits of phase W preload value */
#define MCPWL_CPWL7_OR	(1 << MCPWL_CPWL7)
#define MCPWL_CPWL_OR	((1 << MCPWL_CPWL3)|(1 << MCPWL_CPWL4)\
		|(1 << MCPWL_CPWL5)|(1 << MCPWL_CPWL6)|(1 << MCPWL_CPWL7))

/* Compare Phase V Preload Register High */
STVD7_EXTERN volatile unsigned char MCPVH @0x65;

/* Compare Phase V Preload Register Low */
STVD7_EXTERN volatile unsigned char MCPVL @0x66;
#define MCPVL_CPVL3	3		/* Low bits of phase V preload value */
#define MCPVL_CPVL3_OR	(1 << MCPVL_CPVL3)
#define MCPVL_CPVL4	4		/* Low bits of phase V preload value */
#define MCPVL_CPVL4_OR	(1 << MCPVL_CPVL4)
#define MCPVL_CPVL5	5		/* Low bits of phase V preload value */
#define MCPVL_CPVL5_OR	(1 << MCPVL_CPVL5)
#define MCPVL_CPVL6	6		/* Low bits of phase V preload value */
#define MCPVL_CPVL6_OR	(1 << MCPVL_CPVL6)
#define MCPVL_CPVL7	7		/* Low bits of phase V preload value */
#define MCPVL_CPVL7_OR	(1 << MCPVL_CPVL7)
#define MCPVL_CPVL_OR	((1 << MCPVL_CPVL3)|(1 << MCPVL_CPVL4)\
		|(1 << MCPVL_CPVL5)|(1 << MCPVL_CPVL6)|(1 << MCPVL_CPVL7))

/* Compare Phase U Preload Register High */
STVD7_EXTERN volatile unsigned char MCPUH @0x67;

/* Compare Phase U Preload Register Low */
STVD7_EXTERN volatile unsigned char MCPUL @0x68;
#define MCPUL_CPUL3	3		/* Low bits of phase U preload value */
#define MCPUL_CPUL3_OR	(1 << MCPUL_CPUL3)
#define MCPUL_CPUL4	4		/* Low bits of phase U preload value */
#define MCPUL_CPUL4_OR	(1 << MCPUL_CPUL4)
#define MCPUL_CPUL5	5		/* Low bits of phase U preload value */
#define MCPUL_CPUL5_OR	(1 << MCPUL_CPUL5)
#define MCPUL_CPUL6	6		/* Low bits of phase U preload value */
#define MCPUL_CPUL6_OR	(1 << MCPUL_CPUL6)
#define MCPUL_CPUL7	7		/* Low bits of phase U preload value */
#define MCPUL_CPUL7_OR	(1 << MCPUL_CPUL7)
#define MCPUL_CPUL_OR	((1 << MCPUL_CPUL3)|(1 << MCPUL_CPUL4)\
		|(1 << MCPUL_CPUL5)|(1 << MCPUL_CPUL6)|(1 << MCPUL_CPUL7))

/* Compare Phase O Preload Register High */
STVD7_EXTERN volatile unsigned char MCP0H @0x69;
#define MCP0H_CP0H0	1		/* Most Significant Bits of Compare 0 preload value */
#define MCP0H_CP0H0_OR	(1 << MCP0H_CP0H0)
#define MCP0H_CP0H1	2		/* Most Significant Bits of Compare 0 preload value */
#define MCP0H_CP0H1_OR	(1 << MCP0H_CP0H1)
#define MCP0H_CP0H2	3		/* Most Significant Bits of Compare 0 preload value */
#define MCP0H_CP0H2_OR	(1 << MCP0H_CP0H2)
#define MCP0H_CP0H3	4		/* Most Significant Bits of Compare 0 preload value */
#define MCP0H_CP0H3_OR	(1 << MCP0H_CP0H3)
#define MCP0H_CP0H_OR	((1 << MCP0H_CP0H0)|(1 << MCP0H_CP0H1)\
		|(1 << MCP0H_CP0H2)|(1 << MCP0H_CP0H3))

/* Compare Phase O Preload Register Low */
STVD7_EXTERN volatile unsigned char MCP0L @0x6a;

/* Pwm Auto-Reload Timer (ART) */
/*****************************************************************/

/* Duty Cycle Register 3 */
STVD7_EXTERN volatile unsigned char PWMDCR3 @0x74;

/* Duty Cycle Register 2 */
STVD7_EXTERN volatile unsigned char PWMDCR2 @0x75;

/* Duty Cycle Register 1 */
STVD7_EXTERN volatile unsigned char PWMDCR1 @0x76;

/* Duty Cycle Register 0 */
STVD7_EXTERN volatile unsigned char PWMDCR0 @0x77;

/* PWM Control Register */
STVD7_EXTERN volatile unsigned char PWMCR @0x78;
#define PWMCR_OP0	0		/* PWM Output Polarity */
#define PWMCR_OP0_OR	(1 << PWMCR_OP0)
#define PWMCR_OP1	1		/* PWM Output Polarity */
#define PWMCR_OP1_OR	(1 << PWMCR_OP1)
#define PWMCR_OP2	2		/* PWM Output Polarity */
#define PWMCR_OP2_OR	(1 << PWMCR_OP2)
#define PWMCR_OP3	3		/* PWM Output Polarity */
#define PWMCR_OP3_OR	(1 << PWMCR_OP3)
#define PWMCR_OP_OR	((1 << PWMCR_OP0)|(1 << PWMCR_OP1)\
		|(1 << PWMCR_OP2)|(1 << PWMCR_OP3))
#define PWMCR_OE0	4		/* PWM Output Enable */
#define PWMCR_OE0_OR	(1 << PWMCR_OE0)
#define PWMCR_OE1	5		/* PWM Output Enable */
#define PWMCR_OE1_OR	(1 << PWMCR_OE1)
#define PWMCR_OE2	6		/* PWM Output Enable */
#define PWMCR_OE2_OR	(1 << PWMCR_OE2)
#define PWMCR_OE3	7		/* PWM Output Enable */
#define PWMCR_OE3_OR	(1 << PWMCR_OE3)
#define PWMCR_OE_OR	((1 << PWMCR_OE0)|(1 << PWMCR_OE1)\
		|(1 << PWMCR_OE2)|(1 << PWMCR_OE3))

/* ART Control/Status Register */
STVD7_EXTERN volatile unsigned char ARTCSR @0x79;
#define ARTCSR_OVF	0		/* Overflow Flag */
#define ARTCSR_OVF_OR	(1 << ARTCSR_OVF)
#define ARTCSR_OIE	1		/* Overflow Interrupt Enable */
#define ARTCSR_OIE_OR	(1 << ARTCSR_OIE)
#define ARTCSR_FCRL	2		/* Force Counter Re-Load */
#define ARTCSR_FCRL_OR	(1 << ARTCSR_FCRL)
#define ARTCSR_TCE	3		/* Timer Counter Enable */
#define ARTCSR_TCE_OR	(1 << ARTCSR_TCE)
#define ARTCSR_CC0	4		/* Counter Clock Control */
#define ARTCSR_CC0_OR	(1 << ARTCSR_CC0)
#define ARTCSR_CC1	5		/* Counter Clock Control */
#define ARTCSR_CC1_OR	(1 << ARTCSR_CC1)
#define ARTCSR_CC2	6		/* Counter Clock Control */
#define ARTCSR_CC2_OR	(1 << ARTCSR_CC2)
#define ARTCSR_CC_OR	((1 << ARTCSR_CC0)|(1 << ARTCSR_CC1)\
		|(1 << ARTCSR_CC2))
#define ARTCSR_EXCL	7		/* External Clock */
#define ARTCSR_EXCL_OR	(1 << ARTCSR_EXCL)

/* ART Counter Access Register */
STVD7_EXTERN volatile unsigned char ARTCAR @0x7a;

/* ART Auto-Reload Register */
STVD7_EXTERN volatile unsigned char ARTARR @0x7b;

/* ART Input Capture Control/Status Register */
STVD7_EXTERN volatile unsigned char ARTICCSR @0x7c;
#define ARTICCSR_CF0	0		/* Capture Flag */
#define ARTICCSR_CF0_OR	(1 << ARTICCSR_CF0)
#define ARTICCSR_CF1	1		/* Capture Flag */
#define ARTICCSR_CF1_OR	(1 << ARTICCSR_CF1)
#define ARTICCSR_CF_OR	((1 << ARTICCSR_CF0)|(1 << ARTICCSR_CF1))
#define ARTICCSR_CIE0	2		/* Capture Interrupt Enable */
#define ARTICCSR_CIE0_OR	(1 << ARTICCSR_CIE0)
#define ARTICCSR_CIE1	3		/* Capture Interrupt Enable */
#define ARTICCSR_CIE1_OR	(1 << ARTICCSR_CIE1)
#define ARTICCSR_CIE_OR	((1 << ARTICCSR_CIE0)|(1 << ARTICCSR_CIE1))
#define ARTICCSR_CS0	4		/* Capture Sensitivity */
#define ARTICCSR_CS0_OR	(1 << ARTICCSR_CS0)
#define ARTICCSR_CS1	5		/* Capture Sensitivity */
#define ARTICCSR_CS1_OR	(1 << ARTICCSR_CS1)
#define ARTICCSR_CS_OR	((1 << ARTICCSR_CS0)|(1 << ARTICCSR_CS1))

/* ART Input Capture Register 1 */
STVD7_EXTERN volatile unsigned char ARTICR1 @0x7d;

/* ART Input Capture Register 2 */
STVD7_EXTERN volatile unsigned char ARTICR2 @0x7e;

/* Operational Amplifier (OA) */
/*****************************************************************/

/* Control/Status Register */
STVD7_EXTERN volatile unsigned char OACSR @0x7f;
#define OACSR_HIGHGAIN	7		/* Gain range selection */
#define OACSR_HIGHGAIN_OR	(1 << OACSR_HIGHGAIN)
#define OACSR_OAON	6		/* Amplifier On */
#define OACSR_OAON_OR	(1 << OACSR_OAON)
#define OACSR_AVGCMP	5		/* Average Compensation */
#define OACSR_AVGCMP_OR	(1 << OACSR_AVGCMP)
#define OACSR_OFFCMP	4		/* Offset Compensation */
#define OACSR_OFFCMP_OR	(1 << OACSR_OFFCMP)
#define OACSR_CMPOVR	3		/* Compensation Completed */
#define OACSR_CMPOVR_OR	(1 << OACSR_CMPOVR)

#endif /* __ST7FMC2N6__ */