📄 st7fmc2n6.h
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STVD7_EXTERN volatile unsigned char SICSR_page0 @0x40;
#define SICSR_page0_WDGRF 0 /* Watchdog Reset Flag */
#define SICSR_page0_WDGRF_OR (1 << SICSR_page0_WDGRF)
#define SICSR_page0_CSSD 1 /* Clock Security System Detection */
#define SICSR_page0_CSSD_OR (1 << SICSR_page0_CSSD)
#define SICSR_page0_CSSIE 2 /* Clock Security System Interrupt */
#define SICSR_page0_CSSIE_OR (1 << SICSR_page0_CSSIE)
#define SICSR_page0_LVDRF 4 /* LVD Reset Flag */
#define SICSR_page0_LVDRF_OR (1 << SICSR_page0_LVDRF)
#define SICSR_page0_AVDF 5 /* Voltage Detector Flag */
#define SICSR_page0_AVDF_OR (1 << SICSR_page0_AVDF)
#define SICSR_page0_AVDIE 6 /* Voltage Detector Interrupt */
#define SICSR_page0_AVDIE_OR (1 << SICSR_page0_AVDIE)
#define SICSR_page0_PAGE 7 /* SICSR Register Page Selection */
#define SICSR_page0_PAGE_OR (1 << SICSR_page0_PAGE)
/* System Integrity Control/Status Register (page 1) */
STVD7_EXTERN volatile unsigned char SICSR_page1 @0x40;
#define SICSR_page1_CKSEL 1 /* Clock Source Selection */
#define SICSR_page1_CKSEL_OR (1 << SICSR_page1_CKSEL)
#define SICSR_page1_PLLEN 2 /* PLL Enable */
#define SICSR_page1_PLLEN_OR (1 << SICSR_page1_PLLEN)
#define SICSR_page1_LOCK 4 /* PLL Locked */
#define SICSR_page1_LOCK_OR (1 << SICSR_page1_LOCK)
#define SICSR_page1_VCOEN 5 /* VCO Enable */
#define SICSR_page1_VCOEN_OR (1 << SICSR_page1_VCOEN)
#define SICSR_page1_PAGE 7 /* SICSR Register Page Selection */
#define SICSR_page1_PAGE_OR (1 << SICSR_page1_PAGE)
/* 16-Bit Timer B */
/*****************************************************************/
/* Control Register 2 */
STVD7_EXTERN volatile unsigned char TBCR2 @0x41;
#define TBCR2_EXEDG 0 /* External Clock Edge */
#define TBCR2_EXEDG_OR (1 << TBCR2_EXEDG)
#define TBCR2_IEDG2 1 /* Input Edge 2 */
#define TBCR2_IEDG2_OR (1 << TBCR2_IEDG2)
#define TBCR2_CC0 2 /* Clock Control */
#define TBCR2_CC0_OR (1 << TBCR2_CC0)
#define TBCR2_CC1 3 /* Clock Control */
#define TBCR2_CC1_OR (1 << TBCR2_CC1)
#define TBCR2_CC_OR ((1 << TBCR2_CC0)|(1 << TBCR2_CC1))
#define TBCR2_PWM 4 /* Pulse Width Modulation */
#define TBCR2_PWM_OR (1 << TBCR2_PWM)
#define TBCR2_OPM 5 /* One Pulse Mode */
#define TBCR2_OPM_OR (1 << TBCR2_OPM)
#define TBCR2_OC2E 6 /* Output Compare 2 Output Pin */
#define TBCR2_OC2E_OR (1 << TBCR2_OC2E)
#define TBCR2_OC1E 7 /* Output Compare 1 Output Pin */
#define TBCR2_OC1E_OR (1 << TBCR2_OC1E)
/* Control Register 1 */
STVD7_EXTERN volatile unsigned char TBCR1 @0x42;
#define TBCR1_OLVL1 0 /* Output Level 1 */
#define TBCR1_OLVL1_OR (1 << TBCR1_OLVL1)
#define TBCR1_IEDG1 1 /* Input Edge 1 */
#define TBCR1_IEDG1_OR (1 << TBCR1_IEDG1)
#define TBCR1_OLVL2 2 /* Output Level 2 */
#define TBCR1_OLVL2_OR (1 << TBCR1_OLVL2)
#define TBCR1_FOLV1 3 /* Forced Output Compare 1 */
#define TBCR1_FOLV1_OR (1 << TBCR1_FOLV1)
#define TBCR1_FOLV2 4 /* Forced Output Compare 2 */
#define TBCR1_FOLV2_OR (1 << TBCR1_FOLV2)
#define TBCR1_TOIE 5 /* Timer Overflow Interrupt */
#define TBCR1_TOIE_OR (1 << TBCR1_TOIE)
#define TBCR1_OCIE 6 /* Output Compare Interrupt */
#define TBCR1_OCIE_OR (1 << TBCR1_OCIE)
#define TBCR1_ICIE 7 /* Input Capture Interrupt */
#define TBCR1_ICIE_OR (1 << TBCR1_ICIE)
/* Control/Status Register */
STVD7_EXTERN volatile unsigned char TBCSR @0x43;
#define TBCSR_TIMD 2 /* Timer Disable */
#define TBCSR_TIMD_OR (1 << TBCSR_TIMD)
#define TBCSR_OCF2 3 /* Output Compare Flag 2 */
#define TBCSR_OCF2_OR (1 << TBCSR_OCF2)
#define TBCSR_ICF2 4 /* Input Capture Flag 2 */
#define TBCSR_ICF2_OR (1 << TBCSR_ICF2)
#define TBCSR_TOF 5 /* Timer Overflow */
#define TBCSR_TOF_OR (1 << TBCSR_TOF)
#define TBCSR_OCF1 6 /* Output Compare Flag 1 */
#define TBCSR_OCF1_OR (1 << TBCSR_OCF1)
#define TBCSR_ICF1 7 /* Input Capture Flag 1 */
#define TBCSR_ICF1_OR (1 << TBCSR_ICF1)
/* Input Capture 1 Register */
STVD7_EXTERN volatile unsigned int TBIC1R @0x44;
/* Input Capture 1 High Register */
STVD7_EXTERN volatile unsigned char TBIC1HR @0x44;
/* Input Capture 1 Low Register */
STVD7_EXTERN volatile unsigned char TBIC1LR @0x45;
/* Output Compare 1 Register */
STVD7_EXTERN volatile unsigned int TBOC1R @0x46;
/* Output Compare 1 High Register */
STVD7_EXTERN volatile unsigned char TBOC1HR @0x46;
/* Output Compare 1 Low Register */
STVD7_EXTERN volatile unsigned char TBOC1LR @0x47;
/* Counter Register */
STVD7_EXTERN volatile unsigned int TBCR @0x48;
/* Counter High Register */
STVD7_EXTERN volatile unsigned char TBCHR @0x48;
/* Counter Low Register */
STVD7_EXTERN volatile unsigned char TBCLR @0x49;
/* Alternate Counter Register */
STVD7_EXTERN volatile unsigned int TBACR @0x4a;
/* Alternate Counter High Register */
STVD7_EXTERN volatile unsigned char TBACHR @0x4a;
/* Alternate Counter Low Register */
STVD7_EXTERN volatile unsigned char TBACLR @0x4b;
/* Input Capture 2 Register */
STVD7_EXTERN volatile unsigned int TBIC2R @0x4c;
/* Input Capture 2 High Register */
STVD7_EXTERN volatile unsigned char TBIC2HR @0x4c;
/* Input Capture 2 Low Register */
STVD7_EXTERN volatile unsigned char TBIC2LR @0x4d;
/* Output Compare 2 Register */
STVD7_EXTERN volatile unsigned int TBOC2R @0x4e;
/* Output Compare 2 High Register */
STVD7_EXTERN volatile unsigned char TBOC2HR @0x4e;
/* Output Compare 2 Low Register */
STVD7_EXTERN volatile unsigned char TBOC2LR @0x4f;
/* Motor Controller (MTC) */
/*****************************************************************/
/* MTIM, MDTG - Timer Counter High Register, Dead Time Generator Register */
STVD7_EXTERN volatile unsigned char MTIM @0x50;
STVD7_EXTERN volatile unsigned char MDTG @0x50;
/* MTIML, MPOL - Timer Counter Low Register, Polarity Register */
STVD7_EXTERN volatile unsigned char MTIML @0x51;
STVD7_EXTERN volatile unsigned char MPOL @0x51;
/* MZPRV, MPWME - Capture Zn-1 Register, PWM Register */
STVD7_EXTERN volatile unsigned char MZPRV @0x52;
STVD7_EXTERN volatile unsigned char MPWME @0x52;
/* MZREG, MCONF - Capture Zn Register, Configuration Register */
STVD7_EXTERN volatile unsigned char MZREG @0x53;
STVD7_EXTERN volatile unsigned char MCONF @0x53;
/* MCOMP, MPAR - Compare Cn+1 Register, Parity register */
STVD7_EXTERN volatile unsigned char MCOMP @0x54;
STVD7_EXTERN volatile unsigned char MPAR @0x54;
/* MDREG, MZRF - Demagnetization Register, Z Event Filter Register */
STVD7_EXTERN volatile unsigned char MDREG @0x55;
STVD7_EXTERN volatile unsigned char MZRF @0x55;
/* MWGHT, MSCR - An Weight Register, Sampling Clock Register */
STVD7_EXTERN volatile unsigned char MWGHT @0x56;
STVD7_EXTERN volatile unsigned char MSCR @0x56;
/* Prescaler & Sampling Register */
STVD7_EXTERN volatile unsigned char MPRSR @0x57;
#define MPRSR_ST0 0 /* Step Ratio Max. Min. (Period Range Mini. Max.) */
#define MPRSR_ST0_OR (1 << MPRSR_ST0)
#define MPRSR_ST1 1 /* Step Ratio Max. Min. (Period Range Mini. Max.) */
#define MPRSR_ST1_OR (1 << MPRSR_ST1)
#define MPRSR_ST2 2 /* Step Ratio Max. Min. (Period Range Mini. Max.) */
#define MPRSR_ST2_OR (1 << MPRSR_ST2)
#define MPRSR_ST3 3 /* Step Ratio Max. Min. (Period Range Mini. Max.) */
#define MPRSR_ST3_OR (1 << MPRSR_ST3)
#define MPRSR_ST_OR ((1 << MPRSR_ST0)|(1 << MPRSR_ST1)\
|(1 << MPRSR_ST2)|(1 << MPRSR_ST3))
#define MPRSR_SA0 4 /* Sampling Ratio */
#define MPRSR_SA0_OR (1 << MPRSR_SA0)
#define MPRSR_SA1 5 /* Sampling Ratio */
#define MPRSR_SA1_OR (1 << MPRSR_SA1)
#define MPRSR_SA2 6 /* Sampling Ratio */
#define MPRSR_SA2_OR (1 << MPRSR_SA2)
#define MPRSR_SA3 7 /* Sampling Ratio */
#define MPRSR_SA3_OR (1 << MPRSR_SA3)
#define MPRSR_SA_OR ((1 << MPRSR_SA0)|(1 << MPRSR_SA1)\
|(1 << MPRSR_SA2)|(1 << MPRSR_SA3))
/* Interrupt Mask Register */
STVD7_EXTERN volatile unsigned char MIMR @0x58;
#define MIMR_CIM 0 /* Commutation/Capture Interrupt Mask bit */
#define MIMR_CIM_OR (1 << MIMR_CIM)
#define MIMR_DIM 1 /* End of Demagnetization Interrupt Mask bit */
#define MIMR_DIM_OR (1 << MIMR_DIM)
#define MIMR_ZIM 2 /* Back EMF Zero-crossing Interrupt Mask bit */
#define MIMR_ZIM_OR (1 << MIMR_ZIM)
#define MIMR_EIM 3 /* Emergency stop Interrupt Mask bit */
#define MIMR_EIM_OR (1 << MIMR_EIM)
#define MIMR_CLIM 4 /* Current Limitation Interrupt Mask bit */
#define MIMR_CLIM_OR (1 << MIMR_CLIM)
#define MIMR_RIM 5 /* Ratio update Interrupt Mask bit */
#define MIMR_RIM_OR (1 << MIMR_RIM)
#define MIMR_SEM 6 /* Speed Error Mask bit */
#define MIMR_SEM_OR (1 << MIMR_SEM)
#define MIMR_PUM 7 /* PWM Update Mask bit */
#define MIMR_PUM_OR (1 << MIMR_PUM)
/* Interrupt Status Register */
STVD7_EXTERN volatile unsigned char MISR @0x59;
#define MISR_CI 0 /* Commutation Interrupt flag */
#define MISR_CI_OR (1 << MISR_CI)
#define MISR_DI 1 /* End of Demagnetization Interrupt flag */
#define MISR_DI_OR (1 << MISR_DI)
#define MISR_ZI 2 /* BEMF Zero-crossing Interrupt flag */
#define MISR_ZI_OR (1 << MISR_ZI)
#define MISR_EI 3 /* Emergency Stop Interrupt flag */
#define MISR_EI_OR (1 << MISR_EI)
#define MISR_CLI 4 /* Current Limitation interrupt flag */
#define MISR_CLI_OR (1 << MISR_CLI)
#define MISR_RMI 5 /* Ratio Decrement Interrupt flag */
#define MISR_RMI_OR (1 << MISR_RMI)
#define MISR_RPI 6 /* Ratio Increment Interrupt flag */
#define MISR_RPI_OR (1 << MISR_RPI)
#define MISR_PUI 7 /* PWM Update Interrupt flag */
#define MISR_PUI_OR (1 << MISR_PUI)
/* Control Register A */
STVD7_EXTERN volatile unsigned char MCRA @0x5a;
#define MCRA_DCB 0 /* Data Capture bit */
#define MCRA_DCB_OR (1 << MCRA_DCB)
#define MCRA_PZ 1 /* Protection from parasitic Zero-crossing */
#define MCRA_PZ_OR (1 << MCRA_PZ)
#define MCRA_SWA 2 /* Switched/Autoswitched Mode */
#define MCRA_SWA_OR (1 << MCRA_SWA)
#define MCRA_V0C1 3 /* Voltage/Current Mode */
#define MCRA_V0C1_OR (1 << MCRA_V0C1)
#define MCRA_DAC 4 /* Direct Access to phase state Register */
#define MCRA_DAC_OR (1 << MCRA_DAC)
#define MCRA_SR 5 /* Sensor ON/Off */
#define MCRA_SR_OR (1 << MCRA_SR)
#define MCRA_CKE 6 /* Clock Enable bit */
#define MCRA_CKE_OR (1 << MCRA_CKE)
#define MCRA_MOE 7 /* Output Enable bit */
#define MCRA_MOE_OR (1 << MCRA_MOE)
/* Control Register B */
STVD7_EXTERN volatile unsigned char MCRB @0x5b;
#define MCRB_OS0 0 /* Operating Output mode Selection bit (PWM after Z and before next C) */
#define MCRB_OS0_OR (1 << MCRB_OS0)
#define MCRB_OS1 1 /* Operating Output mode Selection bit (PWM after D and before Z) */
#define MCRB_OS1_OR (1 << MCRB_OS1)
#define MCRB_OS2 2 /* Operating Output mode Selection and preload bit (PWM after C and before D) */
#define MCRB_OS2_OR (1 << MCRB_OS2)
#define MCRB_OCV 3 /* Over Current Handling in Voltage mode */
#define MCRB_OCV_OR (1 << MCRB_OCV)
#define MCRB_SDM 4 /* Simulated Demagnetization event Mask bit */
#define MCRB_SDM_OR (1 << MCRB_SDM)
#define MCRB_HDM 5 /* Hardware Demagnetization event Mask bit */
#define MCRB_HDM_OR (1 << MCRB_HDM)
#define MCRB_CPB 6 /* Compare bit for zero-crossing detection */
#define MCRB_CPB_OR (1 << MCRB_CPB)
/* Control Register C */
STVD7_EXTERN volatile unsigned char MCRC @0x5c;
#define MCRC_VR0 0 /* BEMF/demagnetisation Reference threshold */
#define MCRC_VR0_OR (1 << MCRC_VR0)
#define MCRC_VR1 1 /* BEMF/demagnetisation Reference threshold */
#define MCRC_VR1_OR (1 << MCRC_VR1)
#define MCRC_VR2 2 /* BEMF/demagnetisation Reference threshold */
#define MCRC_VR2_OR (1 << MCRC_VR2)
#define MCRC_VR_OR ((1 << MCRC_VR0)|(1 << MCRC_VR1)\
|(1 << MCRC_VR2))
#define MCRC_SPLG 3 /* Sampling Z event at 1MHz in sensorless mode (SR=0) */
#define MCRC_SPLG_OR (1 << MCRC_SPLG)
#define MCRC_SC 4 /* Simulated commutation event bit */
#define MCRC_SC_OR (1 << MCRC_SC)
#define MCRC_SZ 5 /* Simulated zero-crossing event bit */
#define MCRC_SZ_OR (1 << MCRC_SZ)
#define MCRC_EDIR_HZ 6 /* Encoder Direction bit/Hardware zero-crossing event bit */
#define MCRC_EDIR_HZ_OR (1 << MCRC_EDIR_HZ)
#define MCRC_SEI_OI 7 /* Speed Error interrupt flag/MTIM Overflow flag */
#define MCRC_SEI_OI_OR (1 << MCRC_SEI_OI)
/* Phase State Register */
STVD7_EXTERN volatile unsigned char MPHST @0x5d;
#define MPHST_OO0 0 /* Output Channel 0 On/Off bit */
#define MPHST_OO0_OR (1 << MPHST_OO0)
#define MPHST_OO1 1 /* Output Channel 1 On/Off bit */
#define MPHST_OO1_OR (1 << MPHST_OO1)
#define MPHST_OO2 2 /* Output Channel 2 On/Off bit */
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