📄 st7fmc2n6.h
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#define ISPR1_I0_7_OR (1 << ISPR1_I0_7)
#define ISPR1_I1_7 7 /* MTC C/D IT Priority Level */
#define ISPR1_I1_7_OR (1 << ISPR1_I1_7)
#define ISPR1_I_7_OR ((1 << ISPR1_I0_7)|(1 << ISPR1_I1_7))
/* Interrupt Software Priority Register 2 */
STVD7_EXTERN volatile unsigned char ISPR2 @0x26;
#define ISPR2_I0_8 0 /* SPI IT Priority Level */
#define ISPR2_I0_8_OR (1 << ISPR2_I0_8)
#define ISPR2_I1_8 1 /* SPI IT Priority Level */
#define ISPR2_I1_8_OR (1 << ISPR2_I1_8)
#define ISPR2_I_8_OR ((1 << ISPR2_I0_8)|(1 << ISPR2_I1_8))
#define ISPR2_I0_9 2 /* Timer A IT Priority Level */
#define ISPR2_I0_9_OR (1 << ISPR2_I0_9)
#define ISPR2_I1_9 3 /* Timer A IT Priority Level */
#define ISPR2_I1_9_OR (1 << ISPR2_I1_9)
#define ISPR2_I_9_OR ((1 << ISPR2_I0_9)|(1 << ISPR2_I1_9))
#define ISPR2_I0_10 4 /* Timer B IT Priority Level */
#define ISPR2_I0_10_OR (1 << ISPR2_I0_10)
#define ISPR2_I1_10 5 /* Timer B IT Priority Level */
#define ISPR2_I1_10_OR (1 << ISPR2_I1_10)
#define ISPR2_I_10_OR ((1 << ISPR2_I0_10)|(1 << ISPR2_I1_10))
#define ISPR2_I0_11 6 /* SCI IT Priority Level */
#define ISPR2_I0_11_OR (1 << ISPR2_I0_11)
#define ISPR2_I1_11 7 /* SCI IT Priority Level */
#define ISPR2_I1_11_OR (1 << ISPR2_I1_11)
#define ISPR2_I_11_OR ((1 << ISPR2_I0_11)|(1 << ISPR2_I1_11))
/* Interrupt Software Priority Register 3 */
STVD7_EXTERN volatile unsigned char ISPR3 @0x27;
#define ISPR3_I0_12 0 /* AVD IT Priority Level */
#define ISPR3_I0_12_OR (1 << ISPR3_I0_12)
#define ISPR3_I1_12 1 /* AVD IT Priority Level */
#define ISPR3_I1_12_OR (1 << ISPR3_I1_12)
#define ISPR3_I_12_OR ((1 << ISPR3_I0_12)|(1 << ISPR3_I1_12))
#define ISPR3_I0_13 2 /* PWMART IT Priority Level */
#define ISPR3_I0_13_OR (1 << ISPR3_I0_13)
#define ISPR3_I1_13 3 /* PWMART IT Priority Level */
#define ISPR3_I1_13_OR (1 << ISPR3_I1_13)
#define ISPR3_I_13_OR ((1 << ISPR3_I0_13)|(1 << ISPR3_I1_13))
/* External Interrupt Control Register */
STVD7_EXTERN volatile unsigned char EICR @0x28;
#define EICR_IPA 0 /* Interrupt Polarity port A */
#define EICR_IPA_OR (1 << EICR_IPA)
#define EICR_IS30 1 /* EI0 Sensitivity */
#define EICR_IS30_OR (1 << EICR_IS30)
#define EICR_IS31 2 /* EI0 Sensitivity */
#define EICR_IS31_OR (1 << EICR_IS31)
#define EICR_IS3_OR ((1 << EICR_IS30)|(1 << EICR_IS31))
#define EICR_IS20 3 /* EI1 Sensitivity */
#define EICR_IS20_OR (1 << EICR_IS20)
#define EICR_IS21 4 /* EI1 Sensitivity */
#define EICR_IS21_OR (1 << EICR_IS21)
#define EICR_IS2_OR ((1 << EICR_IS20)|(1 << EICR_IS21))
#define EICR_IPB 5 /* Interrupt Polarity port B */
#define EICR_IPB_OR (1 << EICR_IPB)
#define EICR_IS10 6 /* EI2 Sensitivity */
#define EICR_IS10_OR (1 << EICR_IS10)
#define EICR_IS11 7 /* EI2 Sensitivity */
#define EICR_IS11_OR (1 << EICR_IS11)
#define EICR_IS1_OR ((1 << EICR_IS10)|(1 << EICR_IS11))
/* Flash */
/*****************************************************************/
/* Flash Control/Status Register */
STVD7_EXTERN volatile unsigned char FCSR @0x29;
/* Window Watchdog (WWDG) */
/*****************************************************************/
/* Control Register */
STVD7_EXTERN volatile unsigned char WDGCR @0x2a;
#define WDGCR_WDGA 7 /* Activation Bit */
#define WDGCR_WDGA_OR (1 << WDGCR_WDGA)
#define WDGCR_T0 0 /* 7-bit Timer */
#define WDGCR_T0_OR (1 << WDGCR_T0)
#define WDGCR_T1 1 /* 7-bit Timer */
#define WDGCR_T1_OR (1 << WDGCR_T1)
#define WDGCR_T2 2 /* 7-bit Timer */
#define WDGCR_T2_OR (1 << WDGCR_T2)
#define WDGCR_T3 3 /* 7-bit Timer */
#define WDGCR_T3_OR (1 << WDGCR_T3)
#define WDGCR_T4 4 /* 7-bit Timer */
#define WDGCR_T4_OR (1 << WDGCR_T4)
#define WDGCR_T5 5 /* 7-bit Timer */
#define WDGCR_T5_OR (1 << WDGCR_T5)
#define WDGCR_T6 6 /* 7-bit Timer */
#define WDGCR_T6_OR (1 << WDGCR_T6)
#define WDGCR_T_OR ((1 << WDGCR_T0)|(1 << WDGCR_T1)\
|(1 << WDGCR_T2)|(1 << WDGCR_T3)|(1 << WDGCR_T4)|(1 << WDGCR_T5)\
|(1 << WDGCR_T6))
/* Window Register */
STVD7_EXTERN volatile unsigned char WDGWR @0x2b;
#define WDGWR_W0 0 /* 7-bit window value */
#define WDGWR_W0_OR (1 << WDGWR_W0)
#define WDGWR_W1 1 /* 7-bit window value */
#define WDGWR_W1_OR (1 << WDGWR_W1)
#define WDGWR_W2 2 /* 7-bit window value */
#define WDGWR_W2_OR (1 << WDGWR_W2)
#define WDGWR_W3 3 /* 7-bit window value */
#define WDGWR_W3_OR (1 << WDGWR_W3)
#define WDGWR_W4 4 /* 7-bit window value */
#define WDGWR_W4_OR (1 << WDGWR_W4)
#define WDGWR_W5 5 /* 7-bit window value */
#define WDGWR_W5_OR (1 << WDGWR_W5)
#define WDGWR_W6 6 /* 7-bit window value */
#define WDGWR_W6_OR (1 << WDGWR_W6)
#define WDGWR_W_OR ((1 << WDGWR_W0)|(1 << WDGWR_W1)\
|(1 << WDGWR_W2)|(1 << WDGWR_W3)|(1 << WDGWR_W4)|(1 << WDGWR_W5)\
|(1 << WDGWR_W6))
/* Main Clock Controller (MCC) */
/*****************************************************************/
/* Main Clock Control/Status Register */
STVD7_EXTERN volatile unsigned char MCCSR @0x2c;
#define MCCSR_OIF 0 /* Oscillator Interrupt Flag */
#define MCCSR_OIF_OR (1 << MCCSR_OIF)
#define MCCSR_OIE 1 /* Oscillator Interrupt */
#define MCCSR_OIE_OR (1 << MCCSR_OIE)
#define MCCSR_TB0 2 /* Time Base Control */
#define MCCSR_TB0_OR (1 << MCCSR_TB0)
#define MCCSR_TB1 3 /* Time Base Control */
#define MCCSR_TB1_OR (1 << MCCSR_TB1)
#define MCCSR_TB_OR ((1 << MCCSR_TB0)|(1 << MCCSR_TB1))
#define MCCSR_SMS 4 /* Slow Mode Select */
#define MCCSR_SMS_OR (1 << MCCSR_SMS)
#define MCCSR_CP0 5 /* CPU Clock Prescaler */
#define MCCSR_CP0_OR (1 << MCCSR_CP0)
#define MCCSR_CP1 6 /* CPU Clock Prescaler */
#define MCCSR_CP1_OR (1 << MCCSR_CP1)
#define MCCSR_CP_OR ((1 << MCCSR_CP0)|(1 << MCCSR_CP1))
#define MCCSR_MCO 7 /* Main Clock Out */
#define MCCSR_MCO_OR (1 << MCCSR_MCO)
/* MCC Beep Control Register */
STVD7_EXTERN volatile unsigned char MCCBCR @0x2d;
#define MCCBCR_BC0 0 /* Beep Control */
#define MCCBCR_BC0_OR (1 << MCCBCR_BC0)
#define MCCBCR_BC1 1 /* Beep Control */
#define MCCBCR_BC1_OR (1 << MCCBCR_BC1)
#define MCCBCR_BC_OR ((1 << MCCBCR_BC0)|(1 << MCCBCR_BC1))
#define MCCBCR_ADCIE 2 /* A/D Converter Interrupt Enable */
#define MCCBCR_ADCIE_OR (1 << MCCBCR_ADCIE)
#define MCCBCR_ADSTS 3 /* A/D Converter Sample Time Stretch */
#define MCCBCR_ADSTS_OR (1 << MCCBCR_ADSTS)
/* 10-Bit A/D Converter (ADC) */
/*****************************************************************/
/* Control/Status Register */
STVD7_EXTERN volatile unsigned char ADCCSR @0x2e;
#define ADCCSR_CH0 0 /* Channel Selection */
#define ADCCSR_CH0_OR (1 << ADCCSR_CH0)
#define ADCCSR_CH1 1 /* Channel Selection */
#define ADCCSR_CH1_OR (1 << ADCCSR_CH1)
#define ADCCSR_CH2 2 /* Channel Selection */
#define ADCCSR_CH2_OR (1 << ADCCSR_CH2)
#define ADCCSR_CH3 3 /* Channel Selection */
#define ADCCSR_CH3_OR (1 << ADCCSR_CH3)
#define ADCCSR_CH_OR ((1 << ADCCSR_CH0)|(1 << ADCCSR_CH1)\
|(1 << ADCCSR_CH2)|(1 << ADCCSR_CH3))
#define ADCCSR_ADON 4 /* Start Converter */
#define ADCCSR_ADON_OR (1 << ADCCSR_ADON)
#define ADCCSR_PRSC0 5 /* Clock prescaler selection */
#define ADCCSR_PRSC0_OR (1 << ADCCSR_PRSC0)
#define ADCCSR_PRSC1 6 /* Clock prescaler selection */
#define ADCCSR_PRSC1_OR (1 << ADCCSR_PRSC1)
#define ADCCSR_PRSC_OR ((1 << ADCCSR_PRSC0)|(1 << ADCCSR_PRSC1))
#define ADCCSR_EOC 7 /* End of Conversion */
#define ADCCSR_EOC_OR (1 << ADCCSR_EOC)
/* Data High Register */
STVD7_EXTERN volatile unsigned char ADCDRH @0x2f;
/* Data low Register */
STVD7_EXTERN volatile unsigned char ADCDRL @0x30;
/* 16-Bit Timer A */
/*****************************************************************/
/* Control Register 2 */
STVD7_EXTERN volatile unsigned char TACR2 @0x31;
#define TACR2_EXEDG 0 /* External Clock Edge */
#define TACR2_EXEDG_OR (1 << TACR2_EXEDG)
#define TACR2_IEDG2 1 /* Input Edge 2 */
#define TACR2_IEDG2_OR (1 << TACR2_IEDG2)
#define TACR2_CC0 2 /* Clock Control */
#define TACR2_CC0_OR (1 << TACR2_CC0)
#define TACR2_CC1 3 /* Clock Control */
#define TACR2_CC1_OR (1 << TACR2_CC1)
#define TACR2_CC_OR ((1 << TACR2_CC0)|(1 << TACR2_CC1))
#define TACR2_PWM 4 /* Pulse Width Modulation */
#define TACR2_PWM_OR (1 << TACR2_PWM)
#define TACR2_OPM 5 /* One Pulse Mode */
#define TACR2_OPM_OR (1 << TACR2_OPM)
#define TACR2_OC2E 6 /* Output Compare 2 Output Pin */
#define TACR2_OC2E_OR (1 << TACR2_OC2E)
#define TACR2_OC1E 7 /* Output Compare 1 Output Pin */
#define TACR2_OC1E_OR (1 << TACR2_OC1E)
/* Control Register 1 */
STVD7_EXTERN volatile unsigned char TACR1 @0x32;
#define TACR1_OLVL1 0 /* Output Level 1 */
#define TACR1_OLVL1_OR (1 << TACR1_OLVL1)
#define TACR1_IEDG1 1 /* Input Edge 1 */
#define TACR1_IEDG1_OR (1 << TACR1_IEDG1)
#define TACR1_OLVL2 2 /* Output Level 2 */
#define TACR1_OLVL2_OR (1 << TACR1_OLVL2)
#define TACR1_FOLV1 3 /* Forced Output Compare 1 */
#define TACR1_FOLV1_OR (1 << TACR1_FOLV1)
#define TACR1_FOLV2 4 /* Forced Output Compare 2 */
#define TACR1_FOLV2_OR (1 << TACR1_FOLV2)
#define TACR1_TOIE 5 /* Timer Overflow Interrupt */
#define TACR1_TOIE_OR (1 << TACR1_TOIE)
#define TACR1_OCIE 6 /* Output Compare Interrupt */
#define TACR1_OCIE_OR (1 << TACR1_OCIE)
#define TACR1_ICIE 7 /* Input Capture Interrupt */
#define TACR1_ICIE_OR (1 << TACR1_ICIE)
/* Control/Status Register */
STVD7_EXTERN volatile unsigned char TACSR @0x33;
#define TACSR_TIMD 2 /* Timer Disable */
#define TACSR_TIMD_OR (1 << TACSR_TIMD)
#define TACSR_OCF2 3 /* Output Compare Flag 2 */
#define TACSR_OCF2_OR (1 << TACSR_OCF2)
#define TACSR_ICF2 4 /* Input Capture Flag 2 */
#define TACSR_ICF2_OR (1 << TACSR_ICF2)
#define TACSR_TOF 5 /* Timer Overflow */
#define TACSR_TOF_OR (1 << TACSR_TOF)
#define TACSR_OCF1 6 /* Output Compare Flag 1 */
#define TACSR_OCF1_OR (1 << TACSR_OCF1)
#define TACSR_ICF1 7 /* Input Capture Flag 1 */
#define TACSR_ICF1_OR (1 << TACSR_ICF1)
/* Input Capture 1 Register */
STVD7_EXTERN volatile unsigned int TAIC1R @0x34;
/* Input Capture 1 High Register */
STVD7_EXTERN volatile unsigned char TAIC1HR @0x34;
/* Input Capture 1 Low Register */
STVD7_EXTERN volatile unsigned char TAIC1LR @0x35;
/* Output Compare 1 Register */
STVD7_EXTERN volatile unsigned int TAOC1R @0x36;
/* Output Compare 1 High Register */
STVD7_EXTERN volatile unsigned char TAOC1HR @0x36;
/* Output Compare 1 Low Register */
STVD7_EXTERN volatile unsigned char TAOC1LR @0x37;
/* Counter Register */
STVD7_EXTERN volatile unsigned int TACR @0x38;
/* Counter High Register */
STVD7_EXTERN volatile unsigned char TACHR @0x38;
/* Counter Low Register */
STVD7_EXTERN volatile unsigned char TACLR @0x39;
/* Alternate Counter Register */
STVD7_EXTERN volatile unsigned int TAACR @0x3a;
/* Alternate Counter High Register */
STVD7_EXTERN volatile unsigned char TAACHR @0x3a;
/* Alternate Counter Low Register */
STVD7_EXTERN volatile unsigned char TAACLR @0x3b;
/* Input Capture 2 Register */
STVD7_EXTERN volatile unsigned int TAIC2R @0x3c;
/* Input Capture 2 High Register */
STVD7_EXTERN volatile unsigned char TAIC2HR @0x3c;
/* Input Capture 2 Low Register */
STVD7_EXTERN volatile unsigned char TAIC2LR @0x3d;
/* Output Compare 2 Register */
STVD7_EXTERN volatile unsigned int TAOC2R @0x3e;
/* Output Compare 2 High Register */
STVD7_EXTERN volatile unsigned char TAOC2HR @0x3e;
/* Output Compare 2 Low Register */
STVD7_EXTERN volatile unsigned char TAOC2LR @0x3f;
/* System Integrity Control/Status Register (SICSR) */
/*****************************************************************/
/* System Integrity Control/Status Register (page 0) */
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