st7fmc2n6.h

该程序是ST7MC驱动三洋压缩机（交流）

/* ST7FMC2N6.h */

/* Copyright (c) 2003 STMicroelectronics */

#ifndef __ST7FMC2N6__
#define __ST7FMC2N6__

/* ST7FMC2N6 */

	/* Check MCU name */
	#ifdef MCU_NAME
		#define ST7FMC2N6 1
		#if (MCU_NAME != ST7FMC2N6)
		#error "wrong include file ST7FMC2N6.h for chosen MCU!"
		#endif
	#endif

	#define STVD7_EXTERN
	#ifdef __HIWARE__
	/* Required to avoid errors at link time, as the Metrowerks compiler   */
	/* prohibits multiple definitions of the same variable.                */
	/* In order to define once the registers, add                          */
	/* "#define __DEFINE_REGISTERS_STVD7_INCLUDE__"                        */
	/* before including this file in one of your application files.        */
		#ifndef __DEFINE_REGISTERS_STVD7_INCLUDE__
		#undef STVD7_EXTERN
		#define STVD7_EXTERN extern
		#endif
	#endif

/* Port A */
/*****************************************************************/

/* Data Register */
STVD7_EXTERN volatile unsigned char PADR @0x00;

/* Data Direction Register */
STVD7_EXTERN volatile unsigned char PADDR @0x01;

/* Option Register */
STVD7_EXTERN volatile unsigned char PAOR @0x02;

/* Port B */
/*****************************************************************/

/* Data Register */
STVD7_EXTERN volatile unsigned char PBDR @0x03;

/* Data Direction Register */
STVD7_EXTERN volatile unsigned char PBDDR @0x04;

/* Option Register */
STVD7_EXTERN volatile unsigned char PBOR @0x05;

/* Port C */
/*****************************************************************/

/* Data Register */
STVD7_EXTERN volatile unsigned char PCDR @0x06;

/* Data Direction Register */
STVD7_EXTERN volatile unsigned char PCDDR @0x07;

/* Option Register */
STVD7_EXTERN volatile unsigned char PCOR @0x08;

/* Port D */
/*****************************************************************/

/* Data Register */
STVD7_EXTERN volatile unsigned char PDDR @0x09;

/* Data Direction Register */
STVD7_EXTERN volatile unsigned char PDDDR @0x0a;

/* Option Register */
STVD7_EXTERN volatile unsigned char PDOR @0x0b;

/* Port E */
/*****************************************************************/

/* Data Register */
STVD7_EXTERN volatile unsigned char PEDR @0x0c;

/* Data Direction Register */
STVD7_EXTERN volatile unsigned char PEDDR @0x0d;

/* Option Register */
STVD7_EXTERN volatile unsigned char PEOR @0x0e;

/* Port F */
/*****************************************************************/

/* Data Register */
STVD7_EXTERN volatile unsigned char PFDR @0x0f;

/* Data Direction Register */
STVD7_EXTERN volatile unsigned char PFDDR @0x10;

/* Option Register */
STVD7_EXTERN volatile unsigned char PFOR @0x11;

/* Serial Communication Interface (LinSCI) */
/*****************************************************************/

/* Status Register */
STVD7_EXTERN volatile unsigned char SCISR @0x18;
#define SCISR_PE	0		/* Parity Error */
#define SCISR_PE_OR	(1 << SCISR_PE)
#define SCISR_FE	1		/* Framing Error */
#define SCISR_FE_OR	(1 << SCISR_FE)
#define SCISR_NF	2		/* Noise Flag */
#define SCISR_NF_OR	(1 << SCISR_NF)
#define SCISR_OR_LHE	3		/* Overrun Error/Lin Header Error */
#define SCISR_OR_LHE_OR	(1 << SCISR_OR_LHE)
#define SCISR_IDLE	4		/* Idle line detect */
#define SCISR_IDLE_OR	(1 << SCISR_IDLE)
#define SCISR_RDRF	5		/* Received Data Ready Flag */
#define SCISR_RDRF_OR	(1 << SCISR_RDRF)
#define SCISR_TC	6		/* Transmission Complete */
#define SCISR_TC_OR	(1 << SCISR_TC)
#define SCISR_TDRE	7		/* Transmission Data Register Empty */
#define SCISR_TDRE_OR	(1 << SCISR_TDRE)

/* Data Register */
STVD7_EXTERN volatile unsigned char SCIDR @0x19;

/* SCIBRR, LPR - Baud Rate Register, Lin Prescaler Register */
STVD7_EXTERN volatile unsigned char SCIBRR @0x1a;
STVD7_EXTERN volatile unsigned char LPR @0x1a;

/* Control Register 1 */
STVD7_EXTERN volatile unsigned char SCICR1 @0x1b;
#define SCICR1_R8	7		/* Receive Data Bit 8 */
#define SCICR1_R8_OR	(1 << SCICR1_R8)
#define SCICR1_T8	6		/* Transmit Data Bit 8 */
#define SCICR1_T8_OR	(1 << SCICR1_T8)
#define SCICR1_SCID	5		/* Sci prescaler and outputs enable/disable bit */
#define SCICR1_SCID_OR	(1 << SCICR1_SCID)
#define SCICR1_M	4		/* Word Length */
#define SCICR1_M_OR	(1 << SCICR1_M)
#define SCICR1_WAKE	3		/* Wake-up Method */
#define SCICR1_WAKE_OR	(1 << SCICR1_WAKE)
#define SCICR1_PCE	2		/* Parity Control Enable */
#define SCICR1_PCE_OR	(1 << SCICR1_PCE)
#define SCICR1_PS	1		/* Parity Selection */
#define SCICR1_PS_OR	(1 << SCICR1_PS)
#define SCICR1_PIE	0		/* Parity Interrupt Enable */
#define SCICR1_PIE_OR	(1 << SCICR1_PIE)

/* Control Register 2 */
STVD7_EXTERN volatile unsigned char SCICR2 @0x1c;
#define SCICR2_SBK	0		/* Send Break */
#define SCICR2_SBK_OR	(1 << SCICR2_SBK)
#define SCICR2_RWU	1		/* Receiver Wake-up Mode */
#define SCICR2_RWU_OR	(1 << SCICR2_RWU)
#define SCICR2_RE	2		/* Receiver */
#define SCICR2_RE_OR	(1 << SCICR2_RE)
#define SCICR2_TE	3		/* Transmitter */
#define SCICR2_TE_OR	(1 << SCICR2_TE)
#define SCICR2_ILIE	4		/* Idle Line Interrupt */
#define SCICR2_ILIE_OR	(1 << SCICR2_ILIE)
#define SCICR2_RIE	5		/* Receiver Interrupt */
#define SCICR2_RIE_OR	(1 << SCICR2_RIE)
#define SCICR2_TCIE	6		/* Transmission Complete Interrupt */
#define SCICR2_TCIE_OR	(1 << SCICR2_TCIE)
#define SCICR2_TIE	7		/* Transmitter Interrupt */
#define SCICR2_TIE_OR	(1 << SCICR2_TIE)

/* Control Register 3 */
STVD7_EXTERN volatile unsigned char SCICR3 @0x1d;
#define SCICR3_LSF	0		/* Lin Synch Field State */
#define SCICR3_LSF_OR	(1 << SCICR3_LSF)
#define SCICR3_LHDF	1		/* Lin Header Detection Flag */
#define SCICR3_LHDF_OR	(1 << SCICR3_LHDF)
#define SCICR3_LHIE	2		/* Lin Header Interrupt Enable */
#define SCICR3_LHIE_OR	(1 << SCICR3_LHIE)
#define SCICR3_LHDM	3		/* Lin Header Detection Method */
#define SCICR3_LHDM_OR	(1 << SCICR3_LHDM)
#define SCICR3_LASE	4		/* Lin Auto Synch Enable */
#define SCICR3_LASE_OR	(1 << SCICR3_LASE)
#define SCICR3_LSLV	5		/* Lin Master/Slave Mode */
#define SCICR3_LSLV_OR	(1 << SCICR3_LSLV)
#define SCICR3_LINE	6		/* Lin Mode Enable/disable */
#define SCICR3_LINE_OR	(1 << SCICR3_LINE)
#define SCICR3_LDUM	7		/* Lin Divider Update Method */
#define SCICR3_LDUM_OR	(1 << SCICR3_LDUM)

/* SCIERPR, LHLR - Extended Receive Prescaler Reg., Lin Header Length Register */
STVD7_EXTERN volatile unsigned char SCIERPR @0x1e;
STVD7_EXTERN volatile unsigned char LHLR @0x1e;

/* SCIETPR, LPRF - Extended Transmit Prescaler Reg., Lin Prescaler Fraction Register */
STVD7_EXTERN volatile unsigned char SCIETPR @0x1f;
STVD7_EXTERN volatile unsigned char LPRF @0x1f;

/* Serial Peripheral Interface (SPI) */
/*****************************************************************/

/* Data I/O Register */
STVD7_EXTERN volatile unsigned char SPIDR @0x21;

/* Control Register */
STVD7_EXTERN volatile unsigned char SPICR @0x22;
#define SPICR_SPR0	0		/* Baud Rate */
#define SPICR_SPR0_OR	(1 << SPICR_SPR0)
#define SPICR_SPR1	1		/* Baud Rate */
#define SPICR_SPR1_OR	(1 << SPICR_SPR1)
#define SPICR_SPR2	5		/* Baud Rate */
#define SPICR_SPR2_OR	(1 << SPICR_SPR2)
#define SPICR_SPR_OR	((1 << SPICR_SPR0)|(1 << SPICR_SPR1)\
		|(1 << SPICR_SPR2))
#define SPICR_CPHA	2		/* Clock Phase */
#define SPICR_CPHA_OR	(1 << SPICR_CPHA)
#define SPICR_CPOL	3		/* Clock Polarity */
#define SPICR_CPOL_OR	(1 << SPICR_CPOL)
#define SPICR_MSTR	4		/* Master Bit */
#define SPICR_MSTR_OR	(1 << SPICR_MSTR)
#define SPICR_SPE	6		/* Serial Peripheral Output */
#define SPICR_SPE_OR	(1 << SPICR_SPE)
#define SPICR_SPIE	7		/* Serial Peripheral Interrupt */
#define SPICR_SPIE_OR	(1 << SPICR_SPIE)

/* Control/Status Register */
STVD7_EXTERN volatile unsigned char SPICSR @0x23;
#define SPICSR_SSI	0		/* /SS Internal Mode */
#define SPICSR_SSI_OR	(1 << SPICSR_SSI)
#define SPICSR_SSM	1		/* /SS Mode Selection */
#define SPICSR_SSM_OR	(1 << SPICSR_SSM)
#define SPICSR_SOD	2		/* SPI Output Disable */
#define SPICSR_SOD_OR	(1 << SPICSR_SOD)
#define SPICSR_MODF	4		/* Mode Fault Flag */
#define SPICSR_MODF_OR	(1 << SPICSR_MODF)
#define SPICSR_OVR	5		/* SPI Overrun error */
#define SPICSR_OVR_OR	(1 << SPICSR_OVR)
#define SPICSR_WCOL	6		/* Write Collision Status */
#define SPICSR_WCOL_OR	(1 << SPICSR_WCOL)
#define SPICSR_SPIF	7		/* Data Transfer Flag */
#define SPICSR_SPIF_OR	(1 << SPICSR_SPIF)

/* Interrupt Software Priority (ITC) */
/*****************************************************************/

/* Interrupt Software Priority Register 0 */
STVD7_EXTERN volatile unsigned char ISPR0 @0x24;
#define ISPR0_I0_0	0		/* External Non Maskable IT Priority Level */
#define ISPR0_I0_0_OR	(1 << ISPR0_I0_0)
#define ISPR0_I1_0	1		/* External Non Maskable IT Priority Level */
#define ISPR0_I1_0_OR	(1 << ISPR0_I1_0)
#define ISPR0_I_0_OR	((1 << ISPR0_I0_0)|(1 << ISPR0_I1_0))
#define ISPR0_I0_1	2		/* MCC IT Priority Level */
#define ISPR0_I0_1_OR	(1 << ISPR0_I0_1)
#define ISPR0_I1_1	3		/* MCC IT Priority Level */
#define ISPR0_I1_1_OR	(1 << ISPR0_I1_1)
#define ISPR0_I_1_OR	((1 << ISPR0_I0_1)|(1 << ISPR0_I1_1))
#define ISPR0_I0_2	4		/* External IT 0 Priority Level */
#define ISPR0_I0_2_OR	(1 << ISPR0_I0_2)
#define ISPR0_I1_2	5		/* External IT 0 Priority Level */
#define ISPR0_I1_2_OR	(1 << ISPR0_I1_2)
#define ISPR0_I_2_OR	((1 << ISPR0_I0_2)|(1 << ISPR0_I1_2))
#define ISPR0_I0_3	6		/* External IT 1 Priority Level */
#define ISPR0_I0_3_OR	(1 << ISPR0_I0_3)
#define ISPR0_I1_3	7		/* External IT 1 Priority Level */
#define ISPR0_I1_3_OR	(1 << ISPR0_I1_3)
#define ISPR0_I_3_OR	((1 << ISPR0_I0_3)|(1 << ISPR0_I1_3))

/* Interrupt Software Priority Register 1 */
STVD7_EXTERN volatile unsigned char ISPR1 @0x25;
#define ISPR1_I0_4	0		/* External IT 2 Priority Level */
#define ISPR1_I0_4_OR	(1 << ISPR1_I0_4)
#define ISPR1_I1_4	1		/* External IT 2 Priority Level */
#define ISPR1_I1_4_OR	(1 << ISPR1_I1_4)
#define ISPR1_I_4_OR	((1 << ISPR1_I0_4)|(1 << ISPR1_I1_4))
#define ISPR1_I0_5	2		/* MTC U/CL IT Priority Level */
#define ISPR1_I0_5_OR	(1 << ISPR1_I0_5)
#define ISPR1_I1_5	3		/* MTC U/CL IT Priority Level */
#define ISPR1_I1_5_OR	(1 << ISPR1_I1_5)
#define ISPR1_I_5_OR	((1 << ISPR1_I0_5)|(1 << ISPR1_I1_5))
#define ISPR1_I0_6	4		/* MTC R/Z IT Priority Level */
#define ISPR1_I0_6_OR	(1 << ISPR1_I0_6)
#define ISPR1_I1_6	5		/* MTC R/Z IT Priority Level */
#define ISPR1_I1_6_OR	(1 << ISPR1_I1_6)
#define ISPR1_I_6_OR	((1 << ISPR1_I0_6)|(1 << ISPR1_I1_6))
#define ISPR1_I0_7	6		/* MTC C/D IT Priority Level */