📄 1100.lst
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C51 COMPILER V7.06 1100 12/20/2007 00:40:14 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE 1100
OBJECT MODULE PLACED IN 1100.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE 1100.c BROWSE DEBUG OBJECTEXTEND
stmt level source
1 #include <reg52.h>
2 #include <intrins.h>
3 #define INT8U unsigned char
4 #define INT16U unsigned int
5
6 #define WRITE_BURST 0x40 //连续写入
7 #define READ_SINGLE 0x80 //读
8 #define READ_BURST 0xC0 //连续读
9 #define BYTES_IN_RXFIFO 0x7F //接收缓冲区的有效字节数
10 #define CRC_OK 0x80 //CRC校验通过位标志
11 //*****************************************************************************************
12 sbit GDO0 =P1^3;
13 sbit GDO2 =P3^2;
14 sbit MISO =P1^6;
15 sbit MOSI =P1^5;
16 sbit SCK =P1^7;
17 sbit CSN =P1^2;
18 //*****************************************************************************************
19 sbit KEY1 =P3^6;
20 sbit KEY2 =P3^7;
21 //*****************************************************************************************
22 INT8U PaTabel[8] = {0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60};
23
24 INT8U seg[10]={0xC0,0xCF,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90}; //0~~9段码
25 //*****************************************************************************************
26 void SpiInit(void);
27 void CpuInit(void);
28 void RESET_CC1100(void);
29 void POWER_UP_RESET_CC1100(void);
30 void halSpiWriteReg(INT8U addr, INT8U value);
31 void halSpiWriteBurstReg(INT8U addr, INT8U *buffer, INT8U count);
32 void halSpiStrobe(INT8U strobe);
33 INT8U halSpiReadReg(INT8U addr);
34 void halSpiReadBurstReg(INT8U addr, INT8U *buffer, INT8U count);
35 INT8U halSpiReadStatus(INT8U addr);
36 void halRfWriteRfSettings(void);
37 void halRfSendPacket(INT8U *txBuffer, INT8U size);
38 INT8U halRfReceivePacket(INT8U *rxBuffer, INT8U *length);
39 //*****************************************************************************************
40 // CC1100 STROBE, CONTROL AND STATUS REGSITER
41 #define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
42 #define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
43 #define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
44 #define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
45 #define CCxxx0_SYNC1 0x04 // Sync word, high INT8U
46 #define CCxxx0_SYNC0 0x05 // Sync word, low INT8U
47 #define CCxxx0_PKTLEN 0x06 // Packet length
48 #define CCxxx0_PKTCTRL1 0x07 // Packet automation control
49 #define CCxxx0_PKTCTRL0 0x08 // Packet automation control
50 #define CCxxx0_ADDR 0x09 // Device address
51 #define CCxxx0_CHANNR 0x0A // Channel number
52 #define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
53 #define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
54 #define CCxxx0_FREQ2 0x0D // Frequency control word, high INT8U
55 #define CCxxx0_FREQ1 0x0E // Frequency control word, middle INT8U
C51 COMPILER V7.06 1100 12/20/2007 00:40:14 PAGE 2
56 #define CCxxx0_FREQ0 0x0F // Frequency control word, low INT8U
57 #define CCxxx0_MDMCFG4 0x10 // Modem configuration
58 #define CCxxx0_MDMCFG3 0x11 // Modem configuration
59 #define CCxxx0_MDMCFG2 0x12 // Modem configuration
60 #define CCxxx0_MDMCFG1 0x13 // Modem configuration
61 #define CCxxx0_MDMCFG0 0x14 // Modem configuration
62 #define CCxxx0_DEVIATN 0x15 // Modem deviation setting
63 #define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
64 #define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
65 #define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
66 #define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
67 #define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
68 #define CCxxx0_AGCCTRL2 0x1B // AGC control
69 #define CCxxx0_AGCCTRL1 0x1C // AGC control
70 #define CCxxx0_AGCCTRL0 0x1D // AGC control
71 #define CCxxx0_WOREVT1 0x1E // High INT8U Event 0 timeout
72 #define CCxxx0_WOREVT0 0x1F // Low INT8U Event 0 timeout
73 #define CCxxx0_WORCTRL 0x20 // Wake On Radio control
74 #define CCxxx0_FREND1 0x21 // Front end RX configuration
75 #define CCxxx0_FREND0 0x22 // Front end TX configuration
76 #define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
77 #define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
78 #define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
79 #define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
80 #define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
81 #define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
82 #define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
83 #define CCxxx0_PTEST 0x2A // Production test
84 #define CCxxx0_AGCTEST 0x2B // AGC test
85 #define CCxxx0_TEST2 0x2C // Various test settings
86 #define CCxxx0_TEST1 0x2D // Various test settings
87 #define CCxxx0_TEST0 0x2E // Various test settings
88
89 // Strobe commands
90 #define CCxxx0_SRES 0x30 // Reset chip.
91 #define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL
-=1).
92 // If in RX/TX: Go to a wait state where only the synthesizer is
93 // running (for quick RX / TX turnaround).
94 #define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
95 #define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
96 // (enables quick start).
97 #define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
98 // MCSM0.FS_AUTOCAL=1.
99 #define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
100 // MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
101 // Only go to TX if channel is clear.
102 #define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
103 // Wake-On-Radio mode if applicable.
104 #define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
105 #define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
106 #define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
107 #define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
108 #define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
109 #define CCxxx0_SWORRST 0x3C // Reset real time clock.
110 #define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two
111 // INT8Us for simpler software.
112
113 #define CCxxx0_PARTNUM 0x30
114 #define CCxxx0_VERSION 0x31
115 #define CCxxx0_FREQEST 0x32
116 #define CCxxx0_LQI 0x33
C51 COMPILER V7.06 1100 12/20/2007 00:40:14 PAGE 3
117 #define CCxxx0_RSSI 0x34
118 #define CCxxx0_MARCSTATE 0x35
119 #define CCxxx0_WORTIME1 0x36
120 #define CCxxx0_WORTIME0 0x37
121 #define CCxxx0_PKTSTATUS 0x38
122 #define CCxxx0_VCO_VC_DAC 0x39
123 #define CCxxx0_TXBYTES 0x3A
124 #define CCxxx0_RXBYTES 0x3B
125
126 #define CCxxx0_PATABLE 0x3E
127 #define CCxxx0_TXFIFO 0x3F
128 #define CCxxx0_RXFIFO 0x3F
129
130 // RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers
131 typedef struct S_RF_SETTINGS
132 {
133 INT8U FSCTRL2; //自已加的
134 INT8U FSCTRL1; // Frequency synthesizer control.
135 INT8U FSCTRL0; // Frequency synthesizer control.
136 INT8U FREQ2; // Frequency control word, high INT8U.
137 INT8U FREQ1; // Frequency control word, middle INT8U.
138 INT8U FREQ0; // Frequency control word, low INT8U.
139 INT8U MDMCFG4; // Modem configuration.
140 INT8U MDMCFG3; // Modem configuration.
141 INT8U MDMCFG2; // Modem configuration.
142 INT8U MDMCFG1; // Modem configuration.
143 INT8U MDMCFG0; // Modem configuration.
144 INT8U CHANNR; // Channel number.
145 INT8U DEVIATN; // Modem deviation setting (when FSK modulation is enabled).
146 INT8U FREND1; // Front end RX configuration.
147 INT8U FREND0; // Front end RX configuration.
148 INT8U MCSM0; // Main Radio Control State Machine configuration.
149 INT8U FOCCFG; // Frequency Offset Compensation Configuration.
150 INT8U BSCFG; // Bit synchronization Configuration.
151 INT8U AGCCTRL2; // AGC control.
152 INT8U AGCCTRL1; // AGC control.
153 INT8U AGCCTRL0; // AGC control.
154 INT8U FSCAL3; // Frequency synthesizer calibration.
155 INT8U FSCAL2; // Frequency synthesizer calibration.
156 INT8U FSCAL1; // Frequency synthesizer calibration.
157 INT8U FSCAL0; // Frequency synthesizer calibration.
158 INT8U FSTEST; // Frequency synthesizer calibration control
159 INT8U TEST2; // Various test settings.
160 INT8U TEST1; // Various test settings.
161 INT8U TEST0; // Various test settings.
162 INT8U IOCFG2; // GDO2 output pin configuration
163 INT8U IOCFG0; // GDO0 output pin configuration
164 INT8U PKTCTRL1; // Packet automation control.
165 INT8U PKTCTRL0; // Packet automation control.
166 INT8U ADDR; // Device address.
167 INT8U PKTLEN; // Packet length.
168 } RF_SETTINGS;
169
170 /////////////////////////////////////////////////////////////////
171 const RF_SETTINGS rfSettings =
172 {
173 0x00,
174 0x08, // FSCTRL1 Frequency synthesizer control.
175 0x00, // FSCTRL0 Frequency synthesizer control.
176 0x10, // FREQ2 Frequency control word, high byte.
177 0xA7, // FREQ1 Frequency control word, middle byte.
178 0x62, // FREQ0 Frequency control word, low byte.
C51 COMPILER V7.06 1100 12/20/2007 00:40:14 PAGE 4
179 0x5B, // MDMCFG4 Modem configuration.
180 0xF8, // MDMCFG3 Modem configuration.
181 0x03, // MDMCFG2 Modem configuration.
182 0x22, // MDMCFG1 Modem configuration.
183 0xF8, // MDMCFG0 Modem configuration.
184
185 0x00, // CHANNR Channel number.
186 0x47, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
187 0xB6, // FREND1 Front end RX configuration.
188 0x10, // FREND0 Front end RX configuration.
189 0x18, // MCSM0 Main Radio Control State Machine configuration.
190 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
191 0x1C, // BSCFG Bit synchronization Configuration.
192 0xC7, // AGCCTRL2 AGC control.
193 0x00, // AGCCTRL1 AGC control.
194 0xB2, // AGCCTRL0 AGC control.
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