📄 1100.lst
字号:
C51 COMPILER V7.06 1100 12/19/2007 21:21:42 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE 1100
OBJECT MODULE PLACED IN 1100.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE 1100.c BROWSE DEBUG OBJECTEXTEND
stmt level source
1 #include <reg52.h>
2 #include <intrins.h>
3 #define INT8U unsigned char
4 #define INT16U unsigned int
5
6 #define WRITE_BURST 0x40 //连续写入
7 #define READ_SINGLE 0x80 //读
8 #define READ_BURST 0xC0 //连续读
9 #define BYTES_IN_RXFIFO 0x7F //接收缓冲区的有效字节数
10 #define CRC_OK 0x80 //CRC校验通过位标志
11 //*****************************************************************************************
12 sbit GDO0 =P1^3;
13 sbit GDO2 =P3^2;
14 sbit MISO =P1^6;
15 sbit MOSI =P1^5;
16 sbit SCK =P1^7;
17 sbit CSN =P1^2;
18 //*****************************************************************************************
19 sbit LED2 =P3^4;
20 sbit LED1 =P3^5;
21 sbit KEY1 =P3^6;
22 sbit KEY2 =P3^7;
23 //*****************************************************************************************
24 sbit led3=P2^3;
25 sbit led2=P2^2;
26 sbit led1=P2^1;
27 sbit led0=P2^0;
28 //*****************************************************************************************
29 sbit st=P2^6;
30 //*****************************************************************************************
31 sbit DQ=P2^5 ;
32 //*****************************************************************************************
33 INT8U PaTabel[8] = {0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60};
34 INT8U seg[10]={0xC0,0xCF,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90}; //0~~9段码
35 INT8U seg1[10]={0x40,0x4F,0x24,0x30,0x19,0x12,0x02,0x78,0x00,0x10};
36 INT8U data temp_data[2]={0x00,0x00};
37 INT8U dispaly[8];
38 //*****************************************************************************************
39 void SpiInit(void);
40 void CpuInit(void);
41 void RESET_CC1100(void);
42 void POWER_UP_RESET_CC1100(void);
43 void halSpiWriteReg(INT8U addr, INT8U value);
44 void halSpiWriteBurstReg(INT8U addr, INT8U *buffer, INT8U count);
45 void halSpiStrobe(INT8U strobe);
46 INT8U halSpiReadReg(INT8U addr);
47 void halSpiReadBurstReg(INT8U addr, INT8U *buffer, INT8U count);
48 INT8U halSpiReadStatus(INT8U addr);
49 void halRfWriteRfSettings(void);
50 void halRfSendPacket(INT8U *txBuffer, INT8U size);
51 INT8U halRfReceivePacket(INT8U *rxBuffer, INT8U *length);
52 //*****************************************************************************************
53 void delay1(INT16U i);
54 void ds_reset(void);
55 void write_byte(INT8U value);
C51 COMPILER V7.06 1100 12/19/2007 21:21:42 PAGE 2
56 INT8U read_byte(void);
57 void read_temp();
58 void work_temp();
59 //*****************************************************************************************
60 // CC1100 STROBE, CONTROL AND STATUS REGSITER
61 #define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
62 #define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
63 #define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
64 #define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
65 #define CCxxx0_SYNC1 0x04 // Sync word, high INT8U
66 #define CCxxx0_SYNC0 0x05 // Sync word, low INT8U
67 #define CCxxx0_PKTLEN 0x06 // Packet length
68 #define CCxxx0_PKTCTRL1 0x07 // Packet automation control
69 #define CCxxx0_PKTCTRL0 0x08 // Packet automation control
70 #define CCxxx0_ADDR 0x09 // Device address
71 #define CCxxx0_CHANNR 0x0A // Channel number
72 #define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
73 #define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
74 #define CCxxx0_FREQ2 0x0D // Frequency control word, high INT8U
75 #define CCxxx0_FREQ1 0x0E // Frequency control word, middle INT8U
76 #define CCxxx0_FREQ0 0x0F // Frequency control word, low INT8U
77 #define CCxxx0_MDMCFG4 0x10 // Modem configuration
78 #define CCxxx0_MDMCFG3 0x11 // Modem configuration
79 #define CCxxx0_MDMCFG2 0x12 // Modem configuration
80 #define CCxxx0_MDMCFG1 0x13 // Modem configuration
81 #define CCxxx0_MDMCFG0 0x14 // Modem configuration
82 #define CCxxx0_DEVIATN 0x15 // Modem deviation setting
83 #define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
84 #define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
85 #define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
86 #define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
87 #define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
88 #define CCxxx0_AGCCTRL2 0x1B // AGC control
89 #define CCxxx0_AGCCTRL1 0x1C // AGC control
90 #define CCxxx0_AGCCTRL0 0x1D // AGC control
91 #define CCxxx0_WOREVT1 0x1E // High INT8U Event 0 timeout
92 #define CCxxx0_WOREVT0 0x1F // Low INT8U Event 0 timeout
93 #define CCxxx0_WORCTRL 0x20 // Wake On Radio control
94 #define CCxxx0_FREND1 0x21 // Front end RX configuration
95 #define CCxxx0_FREND0 0x22 // Front end TX configuration
96 #define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
97 #define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
98 #define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
99 #define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
100 #define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
101 #define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
102 #define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
103 #define CCxxx0_PTEST 0x2A // Production test
104 #define CCxxx0_AGCTEST 0x2B // AGC test
105 #define CCxxx0_TEST2 0x2C // Various test settings
106 #define CCxxx0_TEST1 0x2D // Various test settings
107 #define CCxxx0_TEST0 0x2E // Various test settings
108
109 // Strobe commands
110 #define CCxxx0_SRES 0x30 // Reset chip.
111 #define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL
-=1).
112 // If in RX/TX: Go to a wait state where only the synthesizer is
113 // running (for quick RX / TX turnaround).
114 #define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
115 #define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
116 // (enables quick start).
C51 COMPILER V7.06 1100 12/19/2007 21:21:42 PAGE 3
117 #define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
118 // MCSM0.FS_AUTOCAL=1.
119 #define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
120 // MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
121 // Only go to TX if channel is clear.
122 #define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
123 // Wake-On-Radio mode if applicable.
124 #define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
125 #define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
126 #define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
127 #define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
128 #define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
129 #define CCxxx0_SWORRST 0x3C // Reset real time clock.
130 #define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two
131 // INT8Us for simpler software.
132
133 #define CCxxx0_PARTNUM 0x30
134 #define CCxxx0_VERSION 0x31
135 #define CCxxx0_FREQEST 0x32
136 #define CCxxx0_LQI 0x33
137 #define CCxxx0_RSSI 0x34
138 #define CCxxx0_MARCSTATE 0x35
139 #define CCxxx0_WORTIME1 0x36
140 #define CCxxx0_WORTIME0 0x37
141 #define CCxxx0_PKTSTATUS 0x38
142 #define CCxxx0_VCO_VC_DAC 0x39
143 #define CCxxx0_TXBYTES 0x3A
144 #define CCxxx0_RXBYTES 0x3B
145
146 #define CCxxx0_PATABLE 0x3E
147 #define CCxxx0_TXFIFO 0x3F
148 #define CCxxx0_RXFIFO 0x3F
149
150 // RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers
151 typedef struct S_RF_SETTINGS
152 {
153 INT8U FSCTRL2; //自已加的
154 INT8U FSCTRL1; // Frequency synthesizer control.
155 INT8U FSCTRL0; // Frequency synthesizer control.
156 INT8U FREQ2; // Frequency control word, high INT8U.
157 INT8U FREQ1; // Frequency control word, middle INT8U.
158 INT8U FREQ0; // Frequency control word, low INT8U.
159 INT8U MDMCFG4; // Modem configuration.
160 INT8U MDMCFG3; // Modem configuration.
161 INT8U MDMCFG2; // Modem configuration.
162 INT8U MDMCFG1; // Modem configuration.
163 INT8U MDMCFG0; // Modem configuration.
164 INT8U CHANNR; // Channel number.
165 INT8U DEVIATN; // Modem deviation setting (when FSK modulation is enabled).
166 INT8U FREND1; // Front end RX configuration.
167 INT8U FREND0; // Front end RX configuration.
168 INT8U MCSM0; // Main Radio Control State Machine configuration.
169 INT8U FOCCFG; // Frequency Offset Compensation Configuration.
170 INT8U BSCFG; // Bit synchronization Configuration.
171 INT8U AGCCTRL2; // AGC control.
172 INT8U AGCCTRL1; // AGC control.
173 INT8U AGCCTRL0; // AGC control.
174 INT8U FSCAL3; // Frequency synthesizer calibration.
175 INT8U FSCAL2; // Frequency synthesizer calibration.
176 INT8U FSCAL1; // Frequency synthesizer calibration.
177 INT8U FSCAL0; // Frequency synthesizer calibration.
178 INT8U FSTEST; // Frequency synthesizer calibration control
C51 COMPILER V7.06 1100 12/19/2007 21:21:42 PAGE 4
179 INT8U TEST2; // Various test settings.
180 INT8U TEST1; // Various test settings.
181 INT8U TEST0; // Various test settings.
182 INT8U IOCFG2; // GDO2 output pin configuration
183 INT8U IOCFG0; // GDO0 output pin configuration
184 INT8U PKTCTRL1; // Packet automation control.
185 INT8U PKTCTRL0; // Packet automation control.
186 INT8U ADDR; // Device address.
187 INT8U PKTLEN; // Packet length.
188 } RF_SETTINGS;
189
190 /////////////////////////////////////////////////////////////////
191 const RF_SETTINGS rfSettings =
192 {
193 0x00,
194 0x08, // FSCTRL1 Frequency synthesizer control.
195 0x00, // FSCTRL0 Frequency synthesizer control.
196 0x10, // FREQ2 Frequency control word, high byte.
197 0xA7, // FREQ1 Frequency control word, middle byte.
198 0x62, // FREQ0 Frequency control word, low byte.
199 0x5B, // MDMCFG4 Modem configuration.
200 0xF8, // MDMCFG3 Modem configuration.
201 0x03, // MDMCFG2 Modem configuration.
202 0x22, // MDMCFG1 Modem configuration.
203 0xF8, // MDMCFG0 Modem configuration.
204
205 0x00, // CHANNR Channel number.
206 0x47, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
207 0xB6, // FREND1 Front end RX configuration.
208 0x10, // FREND0 Front end RX configuration.
209 0x18, // MCSM0 Main Radio Control State Machine configuration.
210 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
211 0x1C, // BSCFG Bit synchronization Configuration.
212 0xC7, // AGCCTRL2 AGC control.
213 0x00, // AGCCTRL1 AGC control.
214 0xB2, // AGCCTRL0 AGC control.
215
216 0xEA, // FSCAL3 Frequency synthesizer calibration.
217 0x2A, // FSCAL2 Frequency synthesizer calibration.
218 0x00, // FSCAL1 Frequency synthesizer calibration.
219 0x11, // FSCAL0 Frequency synthesizer calibration.
220 0x59, // FSTEST Frequency synthesizer calibration.
221 0x81, // TEST2 Various test settings.
222 0x35, // TEST1 Various test settings.
223 0x09, // TEST0 Various test settings.
224 0x0B, // IOCFG2 GDO2 output pin configuration.
225 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
226
227 0x04, // PKTCTRL1 Packet automation control.
228 0x05, // PKTCTRL0 Packet automation control.
229 0x00, // ADDR Device address.
230 0x0c // PKTLEN Packet length.
231 };
232 //*****************************************************************************************
233 //函数名：delay(unsigned int s)
234 //输入：时间
235 //输出：无
236 //功能描述：普通廷时,内部用
237 //*****************************************************************************************
238 static void delay(unsigned int s)
239 {
C51 COMPILER V7.06 1100 12/19/2007 21:21:42 PAGE 5
240 1 unsigned int i;
241 1 for(i=0; i<s; i++);
242 1 for(i=0; i<s; i++);
243 1 }
244
245
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -