📄 st7mc_hr.h
字号:
@tiny extern volatile u8 ADCCSR; /* ADC Control Status Register */
@tiny extern volatile u8 ADCDRH; /* ADC Data Register High */
@tiny extern volatile u8 ADCDRL; /* ADC Data Register Low */
@tiny extern volatile u8 TACR2; /* timer A control register 2 */
@tiny extern volatile u8 TACR1; /* timer A control register 1 */
@tiny extern volatile u8 TASR; /* timer A status register */
@tiny extern volatile u8 TAIC1HR; /* timer A input capture 1 high register */
@tiny extern volatile u8 TAIC1LR; /* timer A input capture 1 low register */
@tiny extern volatile u8 TAOC1HR; /* timer A output compare 1 high register */
@tiny extern volatile u8 TAOC1LR; /* timer A output compare 1 low register */
@tiny extern volatile u8 TACHR; /* timer A counter high register */
@tiny extern volatile u8 TACLR; /* timer A counter low register */
@tiny extern volatile u8 TAACHR; /* timer A alternate counter high register */
@tiny extern volatile u8 TAACLR; /* timer A alternate counter low register */
@tiny extern volatile u8 TAIC2HR; /* timer A input capture 2 high register */
@tiny extern volatile u8 TAIC2LR; /* timer A input capture 2 low register */
@tiny extern volatile u8 TAOC2HR; /* timer A output compare 2 high register */
@tiny extern volatile u8 TAOC2LR; /* timer A output compare 2 low register */
@tiny extern volatile u8 SICSR; /* System Integrity Control Status Register */
@tiny extern volatile u8 TBCR2; /* timer B control register 2 */
@tiny extern volatile u8 TBCR1; /* timer B control register 1 */
@tiny extern volatile u8 TBSR; /* timer B status register */
@tiny extern volatile u8 TBIC1HR; /* timer B input capture 1 high register */
@tiny extern volatile u8 TBIC1LR; /* timer B input capture 1 low register */
@tiny extern volatile u8 TBOC1HR; /* timer B output compare 1 high register */
@tiny extern volatile u8 TBOC1LR; /* timer B output compare 1 low register */
@tiny extern volatile u8 TBCHR; /* timer B counter high register */
@tiny extern volatile u8 TBCLR; /* timer B counter low register */
@tiny extern volatile u8 TBACHR; /* timer B alternate counter high register */
@tiny extern volatile u8 TBACLR; /* timer B alternate counter low register */
@tiny extern volatile u8 TBIC2HR; /* timer B input capture 2 high register */
@tiny extern volatile u8 TBIC2LR; /* timer B input capture 2 low register */
@tiny extern volatile u8 TBOC2HR; /* timer B output compare 2 high register */
@tiny extern volatile u8 TBOC2LR; /* timer B output compare 2 low register */
@tiny extern volatile u8 DMCR; /* Debug Control Register */
@tiny extern volatile u8 DMSR; /* Debug Status Register */
@tiny extern volatile u8 DMBK1H; /* Debug Breakpoint 1 MSB MSB Register */
@tiny extern volatile u8 DMBK1L; /* Debug Breakpoint 1 MSB MSB Register */
@tiny extern volatile u8 DMBK2H; /* Debug Breakpoint 1 MSB MSB Register */
@tiny extern volatile u8 DMBK2L; /* Debug Breakpoint 1 MSB MSB Register */
@tiny extern volatile u8 PWMDCR3; /* PWM AR Timer Duty Cycle Register 3 */
@tiny extern volatile u8 PWMDCR2; /* PWM AR Timer Duty Cycle Register 2 */
@tiny extern volatile u8 PWMDCR1; /* PWM AR Timer Duty Cycle Register 1 */
@tiny extern volatile u8 PWMDCR0; /* PWM AR Timer Duty Cycle Register 0 */
@tiny extern volatile u8 PWMCR; /* Auto-Reload Timer Control/Status Register */
@tiny extern volatile u8 ARTCSR; /* Auto-Reload Timer Control/Status Register */
@tiny extern volatile u8 ARTCAR; /* Auto-Reload Timer Counter Access Register */
@tiny extern volatile u8 ARTARR; /* Auto-Reload Timer Auto-Reload Register */
@tiny extern volatile u8 ARTICCSR; /* AR Timer Input Capture Control/Status Reg. */
@tiny extern volatile u8 ARTICR1; /* AR Timer Input Capture Register 1 */
@tiny extern volatile u8 ARTICR2; /* AR Timer Input Capture Register 2 */
@tiny extern volatile u8 OACSR; /* Operational Amplifier Control/Status register */
#else
#error"Unsupported Compiler!" // Compiler Defines not found!
#endif
#endif
/*---CONSTANTS---*/
// LinSCI Peripheral
// SCISR
#define SCI_TDRE ((u8)0x80) /* Transmit data bit */
#define SCI_TC ((u8)0x40) /* Transmission complete */
#define SCI_RDRF ((u8)0x20) /* Received data ready */
#define SCI_IDL ((u8)0x10) /* Idle line detected */
#define SCI_OR ((u8)0x08) /* Overrun error */
#define SCI_NF ((u8)0x04) /* Noise flag */
#define SCI_FE ((u8)0x02) /* Framing error */
#define SCI_PE ((u8)0x01) /* Parity error */
// SCICR1
#define SCI_R8 ((u8)0x80) /* Receive data bit 8 */
#define SCI_T8 ((u8)0x40) /* Transmit data bit 8 */
#define SCI_SCID ((u8)0x20) /* Disable for low power consumption */
#define SCI_M ((u8)0x10) /* Word length */
#define SCI_WAKE ((u8)0x08) /* Wake-up method */
#define SCI_PCE ((u8)0x04) /* Parity control enable */
#define SCI_PS ((u8)0x02) /* Parity selection */
#define SCI_PIE ((u8)0x01) /* Parity interrupt enable */
// SCICR2
#define SCI_TIE ((u8)0x80) /* Transmitter interrupt enable */
#define SCI_TCIE ((u8)0x40) /* Transmission complete interrupt enable */
#define SCI_RIE ((u8)0x20) /* Receiver interrupt enable */
#define SCI_ILIE ((u8)0x10) /* Idle line interrupt enable */
#define SCI_TE ((u8)0x08) /* Transmitter enable */
#define SCI_RE ((u8)0x04) /* Receiver enable */
#define SCI_RWU ((u8)0x02) /* Receiver wake-up */
#define SCI_SBK ((u8)0x01) /* Send break */
#define TX_RX_SCIBRR_9600_Bauds 0xd2 /* TX/RX 9600 bauds */
#define TX_RX_SCIBRR_2400_Bauds 0xe4 /* TX/RX 9600 bauds */
#define TX_RX_SCIBRR_57600_Bauds 0x00 /* TX/RX 57600 bauds */
#define TX_ETPR_57600_Bauds 8 /* TX 57600 bauds */
#define RX_ERPR_57600_Bauds 8 /* RX 57600 bauds */
// ADC peripheral
// ADCCSR: ADC Control/Status Register bit definition
#define EOC ((u8)0x07) /* End of Conversion */
#define PRSC1 ((u8)0x06) /* A/D Clock Prescaler */
#define PRSC0 ((u8)0x05) /* A/D Clock Prescaler */
#define ADON ((u8)0x04) /* A/D converter on */
#define CS3 ((u8)0x03) /* ADC Channel selection */
#define CS2 ((u8)0x02) /* ADC Channel selection */
#define CS1 ((u8)0x01) /* ADC Channel selection */
#define CS0 ((u8)0x00) /* ADC Channel selection */
#define EOC_MSK ((u8)0x80) /* End of Conversion Mask */
#define PRSC1_MSK ((u8)0x40) /* A/D Clock Prescaler Mask */
#define PRSC0_MSK ((u8)0x20) /* A/D Clock Prescaler Mask */
#define ADON_MSK ((u8)0x10) /* A/D converter on Mask */
#define CS3_MSK ((u8)0x08) /* ADC Channel selection Mask */
#define CS2_MSK ((u8)0x04) /* ADC Channel selection Mask */
#define CS1_MSK ((u8)0x02) /* ADC Channel selection Mask */
#define CS0_MSK ((u8)0x01) /* ADC Channel selection Mask */
#define PRSC_MASK ((u8)0x00) /* Define here selected prescaler ratio */
#define CONVERT_AIN0 ((u8)ADON_MSK + PRSC_MASK )
#define CONVERT_AIN1 ((u8)ADON_MSK + PRSC_MASK + CS0_MSK )
#define CONVERT_AIN2 ((u8)ADON_MSK + PRSC_MASK + CS1_MSK )
#define CONVERT_AIN3 ((u8)ADON_MSK + PRSC_MASK + CS1_MSK + CS0_MSK )
#define CONVERT_AIN4 ((u8)ADON_MSK + PRSC_MASK + CS2_MSK )
#define CONVERT_AIN5 ((u8)ADON_MSK + PRSC_MASK + CS2_MSK + CS0_MSK )
#define CONVERT_AIN6 ((u8)ADON_MSK + PRSC_MASK + CS2_MSK + CS1_MSK )
#define CONVERT_AIN7 ((u8)ADON_MSK + PRSC_MASK + CS2_MSK + CS1_MSK + CS0_MSK )
#define CONVERT_AIN8 ((u8)ADON_MSK + PRSC_MASK + CS3_MSK )
#define CONVERT_AIN9 ((u8)ADON_MSK + PRSC_MASK + CS3_MSK + CS0_MSK )
#define CONVERT_AIN10 ((u8)ADON_MSK + PRSC_MASK + CS3_MSK + CS1_MSK )
#define CONVERT_AIN11 ((u8)ADON_MSK + PRSC_MASK + CS3_MSK + CS1_MSK + CS0_MSK )
#define CONVERT_AIN12 ((u8)ADON_MSK + PRSC_MASK + CS3_MSK + CS2_MSK )
#define CONVERT_AIN13 ((u8)ADON_MSK + PRSC_MASK + CS3_MSK + CS2_MSK + CS0_MSK )
#define CONVERT_AIN14 ((u8)ADON_MSK + PRSC_MASK + CS3_MSK + CS2_MSK + CS1_MSK )
#define CONVERT_AIN15 ((u8)ADON_MSK + PRSC_MASK + CS3_MSK + CS2_MSK + CS1_MSK + CS0_MSK )
/* Timers A&B Control Register 1 bit definition */
#define ICIE 0x07 // Input capture interrupt enable
#define OCIE 0x06 // Output compare interrupt enable
#define TOIE 0x05 // Timer overflow interrupt enable
#define OLVL2 0x02 // Output level 2
#define IEDG1 0x01 // Input edge 1
#define OLVL1 0x00 // Ouput level 1
/* Timers A&B Control Register 2 bit definition */
#define OC1E 0x07 // Output compare 1 pin
#define OC2E 0x06 // Output compare 1 pin
#define OPM 0x05 // One pulse mode
#define PWM 0x04 // PWM Mode
#define IEDG2 0x01 // Input edge 2
/* Timer A&B Status register bit definition */
#define ICF1 0x07 // Input capture 1 flag
#define OCF1 0x06 // Output compare 1 flag
#define TOF 0x05 // Timer overflow flag
#define ICF2 0x04 // Input capture 2 flag
#define OCF2 0x03 // Output compare 2 flag
/*------------------------------REGISTER BITS DEFINITION---------------------*/
// MCCSR: MCC Status register
#define TB_INT_FLAG ((u8)0x01) /* Time base interrupt flag */
#define TB_INT_EN ((u8)0x02) /* Time Base interrupt enable */
#define TB25MS ((u8)0x0C) /* Time base (Fosc2=8MHz) */
#define TB10MS ((u8)0x08) /* Time base (Fosc2=8MHz) */
#define TB4MS ((u8)0x04) /* Time base (Fosc2=8MHz) */
#define TB2MS ((u8)0x00) /* Time base (Fosc2=8MHz) */
#define SLOW_MODE ((u8)0x10) /* Slow Mode Select */
#define FOSC_2 ((u8)0x00) /* Fcpu = Fosc2/2 */
#define FOSC_4 ((u8)0x20) /* Fcpu = Fosc2/4 */
#define FOSC_8 ((u8)0x40) /* Fcpu = Fosc2/8 */
#define FOSC_16 ((u8)0x60) /* Fcpu = Fosc2/16 */
#define MCO_ENABLE ((u8)0x80) /* Main Clock Out Selection */
// MCCBCR: MCC Beep control register
#define ADSTS ((u8)0x03) /* ADC Converter Sample Time Stretch */
#define ADCIE ((u8)0x02) /* ADC Interrupt Enable */
#define BC1 ((u8)0x01) /* MCC Beep Control */
#define BC0 ((u8)0x00) /* MCC Beep Control */
/*---CONSTANTS---*/
/* OP-AMP: Operational Amplifier */
#define CMPOVR ((u8)0x80) /* Offset Compensation Status bit */
#define OFFCMP ((u8)0x40) /* Offset compensation start bit */
#define AVGCMP ((u8)0x20) /* Average Compensation times selection */
#define OAON ((u8)0x10) /* Op-Amp power on/off bit */
#define HIGHGAIN ((u8)0x08) /* Gain range selection bit */
/* Window Watchdog */
#define WDGA ((u8)0x80)
#endif
/*** (c) 2004 STMicroelectronics ****************** END OF FILE ***/
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -