mtc_hr.h

该程序是ST7MC驱动BLDC120

#define SMPL_15K4		((u8)0x60) 	/* Sampling frequency in current Mode */
#define SMPL_12K5		((u8)0x70) 	/* Sampling frequency in current Mode */
#define SMPL_10K		((u8)0x80) 	/* Sampling frequency in current Mode */
#define SMPL_6K25		((u8)0x90) 	/* Sampling frequency in current Mode */
#define SMPL_3K13		((u8)0xA0) 	/* Sampling frequency in current Mode */
#define SMPL_1K56		((u8)0xB0) 	/* Sampling frequency in current Mode */
#define SMPL_1K25		((u8)0xC0) 	/* Sampling frequency in current Mode */
#define SMPL_961		((u8)0xD0) 	/* Sampling frequency in current Mode */
#define SMPL_625		((u8)0xD0) 	/* Sampling frequency in current Mode */
#define SMPL_390		((u8)0xF0) 	/* Sampling frequency in current Mode */


/* MIMR: MTC Interrupt Mask Register bit definition */

#define PUM    ((u8)0x07)     	/* PWM Update enable bit position */
#define SEM    ((u8)0x06) 	/* Speed Error enable bit position */
#define RIM    ((u8)0x05)  	/* Ratio update Interrupt enable bit position */
#define CLIM   ((u8)0x04)     	/* Current Limitation Interrupt enable bit position */
#define EIM    ((u8)0x03)     	/* Emergency stop Interrupt enable bit position */
#define ZIM    ((u8)0x02)     	/* Back EMF Zero-crossing Interrupt enable bit position */
#define DIM    ((u8)0x01)     	/* End of Demagnetization Interrupt enable bit position */
#define CIM    ((u8)0x00)     	/* Commutation / Capture Interrupt enable bit position */

#define PUM_MSK	((u8)0x80)     	/* PWM Update enable Mask */
#define SEM_MSK	((u8)0x40) 	   	/* Speed Error enable bit Mask*/
#define RIM_MSK	((u8)0x20)      /* Ratio update Interrupt enable Mask */
#define CLIM_MSK ((u8)0x10)		/* Current Limitation Interrupt enable Mask */
#define EIM_MSK	((u8)0x08)     	/* Emergency stop Interrupt enable Mask */
#define ZIM_MSK	((u8)0x04)     	/* Back EMF Zero-crossing Interrupt enable Mask */
#define DIM_MSK	((u8)0x02)     	/* End of Demagnetization Interrupt enable Mask */
#define CIM_MSK	((u8)0x01)     	/* Commutation / Capture Interrupt enable Mask */


/* MPAR: MTC Parity Register */
#define TACHO_RISING	((u8)0x40)	/* Speed Sensor, Rising edge sensitive */
#define TACHO_FALLING	((u8)0x80)	/* Speed Sensor, Falling edge sensitive */
#define TACHO_BOTH_EDGE	((u8)0xC0)	/* Speed Sensor, both edge sensitive */


/* MPOL: MTC Polarity Register bit definition */

#define ZVD		((u8)0x07)		/* Z vs D edge polarity */
#define REO		((u8)0x06)		/* Read on Even or Odd channel */
#define POL_MSK	((u8)0x3F)		/* Polarity bit selection mask */
#define ALL_ACTIVE_HIGH	((u8)0x3F)	/* All switch drivers having positive logic inputs */
#define ALL_ACTIVE_LOW	((u8)0x00)	/* All switch drivers having positive logic inputs */

/* MDFR: MTC D Event Filter Register */
#define D_EVT_SAMPLE_16	((u8)0xf0)		/* active event after 16 consecutive D valid samples */
#define D_EVT_SAMPLE_15	((u8)0xe0)		/* active event after 15 consecutive D valid samples */
#define D_EVT_SAMPLE_14	((u8)0xd0)		/* active event after 14 consecutive D valid samples */
#define D_EVT_SAMPLE_13	((u8)0xc0)		/* active event after 13 consecutive D valid samples */
#define D_EVT_SAMPLE_12	((u8)0xb0)		/* active event after 12 consecutive D valid samples */
#define D_EVT_SAMPLE_11	((u8)0xa0)		/* active event after 11 consecutive D valid samples */
#define D_EVT_SAMPLE_10	((u8)0x90)		/* active event after 10 consecutive D valid samples */
#define D_EVT_SAMPLE_9	((u8)0x80)		/* active event after 9 consecutive D valid samples */
#define D_EVT_SAMPLE_8	((u8)0x70)		/* active event after 8 consecutive D valid samples */
#define D_EVT_SAMPLE_7	((u8)0x60)		/* active event after 7 consecutive D valid samples */
#define D_EVT_SAMPLE_6	((u8)0x50)		/* active event after 6 consecutive D valid samples */
#define D_EVT_SAMPLE_5	((u8)0x40)		/* active event after 5 consecutive D valid samples */
#define D_EVT_SAMPLE_4	((u8)0x30)		/* active event after 4 consecutive D valid samples */
#define D_EVT_SAMPLE_3	((u8)0x20)		/* active event after 3 consecutive D valid samples */
#define D_EVT_SAMPLE_2	((u8)0x10)		/* active event after 2 consecutive D valid samples */
#define D_EVT_SAMPLE_1	((u8)0x00)		/* active event after 1 consecutive D valid samples */

#define D_EVENT_FILT_200us	((u8)0x0f)		/* 200us filter between events */
#define D_EVENT_FILT_180us	((u8)0x0e)		/* 180us filter between events */
#define D_EVENT_FILT_160us	((u8)0x0d)		/* 160us filter between events */
#define D_EVENT_FILT_140us	((u8)0x0c)		/* 140us filter between events */
#define D_EVENT_FILT_120us	((u8)0x0b)		/* 120us filter between events */
#define D_EVENT_FILT_100us	((u8)0x0a)		/* 100us filter between events */
#define D_EVENT_FILT_80us	((u8)0x09)		/* 80us filter between events */
#define D_EVENT_FILT_60us	((u8)0x08)		/* 60us filter between events */
#define D_EVENT_FILT_40us	((u8)0x07)		/* 40us filter between events */
#define D_EVENT_FILT_35us	((u8)0x06)		/* 35us filter between events */
#define D_EVENT_FILT_30us	((u8)0x05)		/* 30us filter between events */
#define D_EVENT_FILT_25us	((u8)0x04)		/* 25us filter between events */
#define D_EVENT_FILT_20us	((u8)0x03)		/* 20us filter between events */
#define D_EVENT_FILT_15us	((u8)0x02)		/* 15us filter between events */
#define D_EVENT_FILT_10us	((u8)0x01)		/* 10us filter between events */
#define D_EVENT_FILT_5us	((u8)0x00)		/* 5us filter between events */


/* MZFR: MTC Current feedback Filter Register */
#define Z_EVT_SAMPLE_16	((u8)0xf0)		/* active event after 16 consecutive D valid samples */
#define Z_EVT_SAMPLE_15	((u8)0xe0)		/* active event after 15 consecutive D valid samples */
#define Z_EVT_SAMPLE_14	((u8)0xd0)		/* active event after 14 consecutive D valid samples */
#define Z_EVT_SAMPLE_13	((u8)0xc0)		/* active event after 13 consecutive D valid samples */
#define Z_EVT_SAMPLE_12	((u8)0xb0)		/* active event after 12 consecutive D valid samples */
#define Z_EVT_SAMPLE_11	((u8)0xa0)		/* active event after 11 consecutive D valid samples */
#define Z_EVT_SAMPLE_10	((u8)0x90)		/* active event after 10 consecutive D valid samples */
#define Z_EVT_SAMPLE_9	((u8)0x80)		/* active event after 9 consecutive D valid samples */
#define Z_EVT_SAMPLE_8	((u8)0x70)		/* active event after 8 consecutive D valid samples */
#define Z_EVT_SAMPLE_7	((u8)0x60)		/* active event after 7 consecutive D valid samples */
#define Z_EVT_SAMPLE_6	((u8)0x50)		/* active event after 6 consecutive D valid samples */
#define Z_EVT_SAMPLE_5	((u8)0x40)		/* active event after 5 consecutive D valid samples */
#define Z_EVT_SAMPLE_4	((u8)0x30)		/* active event after 4 consecutive D valid samples */
#define Z_EVT_SAMPLE_3	((u8)0x20)		/* active event after 3 consecutive D valid samples */
#define Z_EVT_SAMPLE_2	((u8)0x10)		/* active event after 2 consecutive D valid samples */
#define Z_EVT_SAMPLE_1	((u8)0x00)		/* active event after 1 consecutive D valid samples */

#define Z_EVENT_FILT_200us	((u8)0x0f)		/* 200us filter between events */
#define Z_EVENT_FILT_180us	((u8)0x0e)		/* 180us filter between events */
#define Z_EVENT_FILT_160us	((u8)0x0d)		/* 160us filter between events */
#define Z_EVENT_FILT_140us	((u8)0x0c)		/* 140us filter between events */
#define Z_EVENT_FILT_120us	((u8)0x0b)		/* 120us filter between events */
#define Z_EVENT_FILT_100us	((u8)0x0a)		/* 100us filter between events */
#define Z_EVENT_FILT_80us	((u8)0x09)		/* 80us filter between events */
#define Z_EVENT_FILT_60us	((u8)0x08)		/* 60us filter between events */
#define Z_EVENT_FILT_40us	((u8)0x07)		/* 40us filter between events */
#define Z_EVENT_FILT_35us	((u8)0x06)		/* 35us filter between events */
#define Z_EVENT_FILT_30us	((u8)0x05)		/* 30us filter between events */
#define Z_EVENT_FILT_25us	((u8)0x04)		/* 25us filter between events */
#define Z_EVENT_FILT_20us	((u8)0x03)		/* 20us filter between events */
#define Z_EVENT_FILT_15us	((u8)0x02)		/* 15us filter between events */
#define Z_EVENT_FILT_10us	((u8)0x01)		/* 10us filter between events */
#define Z_EVENT_FILT_5us	((u8)0x00)		/* 5us filter between events */


/* MCFR: MTC Current feedback Filter Register */
#define RPGS	((u8)0x07)		/* Register page selection */
#define RST		((u8)0x06)     	/* Reset MTC peripheral */

#define CURRENT_FD_SAMPLE_8	((u8)0x38)		/* active event after 8 consecutive valid samples */
#define CURRENT_FD_SAMPLE_7	((u8)0x30)		/* active event after 7 consecutive valid samples */
#define CURRENT_FD_SAMPLE_6	((u8)0x28)		/* active event after 6 consecutive valid samples */
#define CURRENT_FD_SAMPLE_5	((u8)0x20)		/* active event after 5 consecutive valid samples */
#define CURRENT_FD_SAMPLE_4	((u8)0x18)		/* active event after 4 consecutive valid samples */
#define CURRENT_FD_SAMPLE_3	((u8)0x10)		/* active event after 3 consecutive valid samples */
#define CURRENT_FD_SAMPLE_2	((u8)0x08)		/* active event after 2 consecutive valid samples */
#define CURRENT_FD_SAMPLE_1	((u8)0x00)		/* active event after 1 consecutive valid sample  */

#define CURRENT_FILT_3us5	((u8)0x07)		/* 3.5us Current filter */
#define CURRENT_FILT_3us	((u8)0x06)		/* 3us   Current filter */
#define CURRENT_FILT_2us5	((u8)0x05)		/* 2.5us Current filter */
#define CURRENT_FILT_2us	((u8)0x04)		/* 2us   Current filter */
#define CURRENT_FILT_1us5	((u8)0x03)		/* 1.5us Current filter */
#define CURRENT_FILT_1us	((u8)0x02)		/* 1us   Current filter */
#define CURRENT_FILT_0us5	((u8)0x01)		/* 0.5us Current filter */
#define CURRENT_FILT_OFF	((u8)0x00)		/* Current filter OFF */


/* MSCR: MTC Sampling Clock Register */
#define ZSV		((u8)0x07)		/* Z event sampling validation */
#define ECM		((u8)0x01)		/* Encoder Capture Mode */
#define DISS	((u8)0x00)		/* Data Input Selection */

#define SAMPLING_CLK_1MHZ	((u8)0x00)		/* 1 Mhz sampling clock frequency */
#define SAMPLING_CLK_500KHZ	((u8)0x04)		/* 500 Khz sampling clock frequency */
#define SAMPLING_CLK_250KHZ	((u8)0x08)		/* 250 Khz sampling clock frequency */
#define SAMPLING_CLK_125KHZ	((u8)0x0c)		/* 125 Khz sampling clock frequency */


/* MREF: MTC Reference Register bit definition */

#define HST		((u8)0x07)		/* Hysteresis comparator value */
#define CL		((u8)0x06)		/* Current loop comparator value */
#define CFAV	((u8)0x05)		/* Current Feedback Amplifier entry Validation */
#define HFE1	((u8)0x04)		/* Chopping mode direction selection */
#define HFE0	((u8)0x03)		/* Chopping mode direction selection */
#define HFRQ2	((u8)0x02)		/* Chopping frequency selection */
#define HFRQ1	((u8)0x01)		/* Chopping frequency selection */
#define HFRQ0	((u8)0x00)		/* Chopping frequency selection */

#define HFEMASK	((u8)0x18)		/* Chopping mode direction selection mask */
#define HFRMASK ((u8)0x07)		/* Chopping frequency selection mask */

#define HST_MASK	((u8)0x80)		/* Hysteresis   comparator value */
#define CL_MASK		((u8)0x40)		/* Current loop comparator value */
#define CFAV_MASK	((u8)0x20)		/* Current Feedback Amplifier entry Validation */

/* MDTG: MTC Dead Time Generator Register bit definition*/

#define PCN		((u8)0x07)		/* PWM Channel number/motor select */ 
#define DTE		((u8)0x06)		/* Dead Time Generator Enable */


/* MPWME: MTC PWM Enable Register bit definition*/

#define DG		((u8)0x07)		/* Debug option	*/ 
#define MPWMW	((u8)0x06)		/* PWM W output control bit */
#define MPWMV	((u8)0x05)		/* PWM W output control bit */
#define MPWMU	((u8)0x04)		/* PWM W output control bit */

#define DG_MSK		((u8)0x80)		/* Debug option	Mask */ 
#define MPWMW_MSK	((u8)0x40)		/* PWM W output control bit Mask */
#define MPWMV_MSK	((u8)0x20)		/* PWM W output control bit Mask */
#define MPWMU_MSK	((u8)0x10)		/* PWM W output control bit Mask */

#define T_OFF_2us5		((u8)0x00)	/* 2.5us Min Off Time in current mode */
#define T_OFF_5us		((u8)0x01)	/* 5us Min Off Time in current mode */
#define T_OFF_7us5		((u8)0x02)	/* 7.5us Min Off Time in current mode */
#define T_OFF_10us		((u8)0x03)	/* 10us Min Off Time in current mode */
#define T_OFF_12us5		((u8)0x04)	/* 12.5us Min Off Time in current mode */
#define T_OFF_15us		((u8)0x05)	/* 15us Min Off Time in current mode */
#define T_OFF_17us5		((u8)0x06)	/* 17.5us Min Off Time in current mode */
#define T_OFF_20us		((u8)0x07)	/* 20us Min Off Time in current mode */
#define T_OFF_22us5		((u8)0x08)	/* 22.5us Min Off Time in current mode */
#define T_OFF_25us		((u8)0x09)	/* 25us Min Off Time in current mode */
#define T_OFF_27us5		((u8)0x0A)	/* 27.5us Min Off Time in current mode */
#define T_OFF_30us		((u8)0x0B)	/* 30us Min Off Time in current mode */
#define T_OFF_32us5		((u8)0x0C)	/* 32.5us Min Off Time in current mode */
#define T_OFF_35us		((u8)0x0D)	/* 35us Min Off Time in current mode */
#define T_OFF_37us5		((u8)0x0E)	/* 37.5us Min Off Time in current mode */
#define T_OFF_40us		((u8)0x0F)	/* 40us Min Off Time in current mode */

/* MPCR: MTC PWM Control Register bit definition*/
#define PMS		((u8)0x07)		/* PWM Mode selection */
#define OVFU	((u8)0x06)		/* Phase U 100% duty cycle */
#define OVFV	((u8)0x05)		/* Phase U 100% duty cycle */
#define OVFW	((u8)0x04)		/* Phase U 100% duty cycle */
#define CMS		((u8)0x03)		/* PWM Counter Mode Selection */
#define PCP2	((u8)0x02)		/* Bit 2 of PWM Counter prescaler */
#define PCP1	((u8)0x01)		/* Bit 1 of PWM Counter prescaler */
#define PCP0	((u8)0x00)		/* Bit 0 of PWM Counter prescaler */

#define PMS_MSK		((u8)0x80)		/* PWM Mode selection mask */
#define CMS_MSK		((u8)0x08)		/* PWM Counter Mode Selection mask */
#define PCP2_MSK	((u8)0x04)		/* Bit 2 of PWM Counter prescaler */
#define PCP1_MSK	((u8)0x02)		/* Bit 1 of PWM Counter prescaler */
#define PCP0_MSK	((u8)0x01)		/* Bit 0 of PWM Counter prescaler */
#define PCPMASK		((u8)0x07)		/* PCP[2:0] bits mask */


/* MCONF: MTC Configuration Register bit definition*/  
#define SOI	    ((u8)0x03)		/*Sampling Out IT flag */
#define SOM	    ((u8)0x02)		/*Sampling Out IT mask bit */
#define XT16	((u8)0x01)		/*Peripheral frequency is Fmtc/4 */ 
#define XT8	    ((u8)0x00)		/*Peripheral frequency	is Fmtc/2 if this bit is set */

#define SOI_MSK	    ((u8)0x08)	/*Sampling Out IT flag mask */
#define SOM_MSK	    ((u8)0x04)	/*Sampling Out IT enable bit mask */
#define XT16_MSK	((u8)0x02)	/* Fmtc/4 enable mask*/
#define XT8_MSK		((u8)0x01)	/* Fmtc/2 enable mask*/

#endif


/*** (c) 2004  STMicroelectronics ****************** END OF FILE ***/