📄 dm7520_reg.h
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/* FILE NAME: dm7520_reg.h FILE DESCRIPTION: This file contains register definitions for DM7520 devices. PROJECT NAME: Linux DM7520 Driver, Library, and Example Programs PROJECT VERSION: (Defined in README.TXT) Copyright 2004 RTD Embedded Technologies, Inc. All Rights Reserved.*/#ifndef DM7520_REG_H#define DM7520_REG_H//// "Helper" constants for register masking//#define BIT_00 0x00000001
#define BIT_01 0x00000002
#define BIT_02 0x00000004
#define BIT_03 0x00000008
#define BIT_04 0x00000010
#define BIT_05 0x00000020
#define BIT_06 0x00000040
#define BIT_07 0x00000080
#define BIT_08 0x00000100
#define BIT_09 0x00000200
#define BIT_10 0x00000400
#define BIT_11 0x00000800
#define BIT_12 0x00001000
#define BIT_13 0x00002000
#define BIT_14 0x00004000
#define BIT_15 0x00008000
#define BIT_16 0x00010000
#define BIT_17 0x00020000
#define BIT_18 0x00040000
#define BIT_19 0x00080000
#define BIT_20 0x00100000
#define BIT_21 0x00200000
#define BIT_22 0x00400000
#define BIT_23 0x00800000
#define BIT_24 0x01000000
#define BIT_25 0x02000000
#define BIT_26 0x04000000
#define BIT_27 0x08000000
#define BIT_28 0x10000000
#define BIT_29 0x20000000
#define BIT_30 0x40000000
#define BIT_31 0x80000000
//
// LAS0
//
//
// LAS0 Runtime Area Read Function Write Function Local Address Space 0 Offset
// -----------------------------------------------------------------
#define LAS0_MT_MODE 0 //0x0000 // Master/Target Only Mode Jumper#define LAS0_SPARE_04 1 //0x0004 // - -
#define LAS0_USER_IO 2 //0x0008 // Read User Inputs Write User Outputs
#define LAS0_DAC_CLK_ST 3 //0x000C // DAC Clock start DAC Clock stop
#define LAS0_ADC 4 //0x0010 // Read FIFO Status Software A/D Start
#define LAS0_DAC1 5 //0x0014 // - Software D/A1 Update
#define LAS0_DAC2 6 //0x0018 // - Software D/A2 Update
#define LAS0_SPARE_1C 7 //0x001C // - -
#define LAS0_SPARE_20 8 //0x0020 // - -
#define LAS0_DAC 9 //0x0024 // - Software Simultaneous D/A1 and D/A2 Update
#define LAS0_PACER 10 //0x0028 // Software Pacer Start Software Pacer Stop
#define LAS0_TIMER 11 //0x002C // Read Timer Counters Status HDIN Software Trigger
#define LAS0_IT 12 //0x0030 // Read Interrupt Status Write Interrupt Enable Mask Register
#define LAS0_CLEAR 13 //0x0034 // Clear ITs set by Clear Mask Set Interrupt Clear Mask
#define LAS0_OVERRUN 14 //0x0038 // Read pending interrupts Clear Overrun Register
#define LAS0_SPARE_3C 15 //0x003C // - -
//
// LAS0 Runtime Area Timer/Counter,Dig.IO Read Function Write Function
// -----------------------------------------------------------------
#define LAS0_PCLK 16 //0x0040 // Pacer Clock value (24bit) Pacer Clock load (24bit)
#define LAS0_BCLK 17 //0x0044 // Burst Clock value (10bit) Burst Clock load (10bit)
#define LAS0_ADC_SCNT 18 //0x0048 // A/D Sample counter value (10bit) A/D Sample counter load (10bit)
#define LAS0_DAC1_UCNT 19 //0x004C // D/A1 Update counter value (10 bit) D/A1 Update counter load (10bit)
#define LAS0_DAC2_UCNT 20 //0x0050 // D/A2 Update counter value (10 bit) D/A2 Update counter load (10bit)
#define LAS0_DCNT 21 //0x0054 // Delay counter value (16 bit) Delay counter load (16bit)
#define LAS0_ACNT 22 //0x0058 // About counter value (16 bit) About counter load (16bit)
#define LAS0_DAC_CLK 23 //0x005C // DAC clock value (16bit) DAC clock load (16bit)
#define LAS0_UTC0 24 //0x0060 // 8254 TC Counter 0 User TC 0 value Load count in TC Counter 0
#define LAS0_UTC1 25 //0x0064 // 8254 TC Counter 1 User TC 1 value Load count in TC Counter 1
#define LAS0_UTC2 26 //0x0068 // 8254 TC Counter 2 User TC 2 value Load count in TC Counter 2
#define LAS0_UTC_CTRL 27 //0x006C // 8254 TC Control Word Program counter mode for TC
#define LAS0_DIO0 28 //0x0070 // Digital I/O Port 0 Read Port Digital I/O Port 0 Write Port
#define LAS0_DIO1 29 //0x0074 // Digital I/O Port 1 Read Port Digital I/O Port 1 Write Port
#define LAS0_DIO0_CTRL 30 //0x0078 // Clear digital IRQ status flag/read Clear digital chip/program Port 0
// // Port0 direction/mask/compare register direction, mask or compare register
#define LAS0_DIO_STATUS 31 //0x007C // Read Digital I/O Status word Program digital control register &
// // digital interrupt enable
//
// LAS0 Setup Area Function
// -----------------------------------------------------------------
#define LAS0_BOARD_RESET 64 //0x0100 // Board reset
#define LAS0_DMA0_SRC 65 //0x0104 // Demand Mode DMA 0 Sources select
#define LAS0_DMA1_SRC 66 //0x0108 // Demand Mode DMA 1 Sources select
#define LAS0_ADC_CONVERSION 67 //0x010C // A/D Conversion Signal select
#define LAS0_BURST_START 68 //0x0110 // Burst Clock Start Trigger select
#define LAS0_PACER_START 69 //0x0114 // Pacer Clock Start Trigger select
#define LAS0_PACER_STOP 70 //0x0118 // Pacer Clock Stop Trigger select
#define LAS0_ACNT_STOP_ENABLE 71 //0x011C // About Counter Stop Enable
#define LAS0_PACER_REPEAT 72 //0x0120 // Pacer Start Trigger Mode select
#define LAS0_DIN_START 73 //0x0124 // High Speed Digital Input Sampling Signal select
#define LAS0_DIN_FIFO_CLEAR 74 //0x0128 // Digital Input FIFO Clear
#define LAS0_ADC_FIFO_CLEAR 75 //0x012C // A/D FIFO Clear
#define LAS0_CGT_WRITE 76 //0x0130 // Channel Gain Table Write
#define LAS0_CGL_WRITE 77 //0x0134 // Channel Gain Latch Write
#define LAS0_CG_DATA 78 //0x0138 // Digital Table Write
#define LAS0_CG_CONTROL 79 //0x013C // Channel Gain Table Enable
#define LAS0_CG_ENABLE 80 //0x0140 // Digital Table Enable
#define LAS0_CGT_PAUSE 81 //0x0144 // Table Pause Enable
#define LAS0_CGT_RESET 82 //0x0148 // Reset Channel Gain Table
#define LAS0_CGT_CLEAR 83 //0x014C // Clear Channel Gain Table
#define LAS0_DAC1_CTRL 84 //0x0150 // D/A1 output type/range
#define LAS0_DAC1_SRC 85 //0x0154 // D/A1 update source
#define LAS0_DAC1_CYCLE 86 //0x0158 // D/A1 cycle mode
#define LAS0_DAC1_RESET 87 //0x015C // D/A1 FIFO reset
#define LAS0_DAC1_FIFO_CLEAR 88 //0x0160 // D/A1 FIFO clear
#define LAS0_DAC2_CTRL 89 //0x0164 // D/A2 output type/range
#define LAS0_DAC2_SRC 90 //0x0168 // D/A2 update source
#define LAS0_DAC2_CYCLE 91 //0x016C // D/A2 cycle mode
#define LAS0_DAC2_RESET 92 //0x0170 // D/A2 FIFO reset
#define LAS0_DAC2_FIFO_CLEAR 93 //0x0174 // D/A2 FIFO clear
#define LAS0_ADC_SCNT_SRC 94 //0x0178 // A/D Sample Counter Source select
#define LAS0_PACER_SELECT 96 //0x0180 // Pacer Clock select
#define LAS0_SBUS0_SRC 97 //0x0184 // SyncBus 0 Source select
#define LAS0_SBUS0_ENABLE 98 //0x0188 // SyncBus 0 enable
#define LAS0_SBUS1_SRC 99 //0x018C // SyncBus 1 Source select
#define LAS0_SBUS1_ENABLE 100 //0x0190 // SyncBus 1 enable
#define LAS0_SBUS2_SRC 102 //0x0198 // SyncBus 2 Source select
#define LAS0_SBUS2_ENABLE 103 //0x019C // SyncBus 2 enable
#define LAS0_ETRG_POLARITY 105 //0x01A4 // External Trigger polarity select
#define LAS0_EINT_POLARITY 106 //0x01A8 // External Interrupt polarity select
#define LAS0_UTC0_CLOCK 107 //0x01AC // UTC0 Clock select
#define LAS0_UTC0_GATE 108 //0x01B0 // UTC0 Gate select
#define LAS0_UTC1_CLOCK 109 //0x01B4 // UTC1 Clock select
#define LAS0_UTC1_GATE 110 //0x01B8 // UTC1 Gate select
#define LAS0_UTC2_CLOCK 111 //0x01BC // UTC2 Clock select
#define LAS0_UTC2_GATE 112 //0x01C0 // UTC2 Gate select
#define LAS0_UOUT0_SELECT 113 //0x01C4 // User Output 0 source select
#define LAS0_UOUT1_SELECT 114 //0x01C8 // User Output 1 source select
#define LAS0_DMA0_RST 115 //0x01CC // DMA0 Request state machine reset
#define LAS0_DMA1_RST 116 //0x01D0 // DMA1 Request state machine reset
#define LAS0_DAC_CLK_START 117 //0x01D4 // D/A clock start select
#define LAS0_DAC_CLK_STOP 118 //0x01D8 // D/A clock stop select
#define LAS0_PACER_CLK_SRC_SEL 119 //0x01DC // Pacer Clock Primary frequency Select
#define LAS0_BURST_CLK_SRC_SEL 120 //0x01E0 // Burst Clock Primary frequency Select
#define LAS0_DAC_CLK_SRC_SEL 121 //0x01E4 // DAC Clock Primary frequency Select
#define LAS0_DAC_CLK_MODE 122 //0x01E8 // D/A clock free-run or start-stop mode select
#define LAS0_MCBSP_AD_CTRL 123 //0x01EC // McBSP A/D FIFO Control
#define LAS0_MCBSP_DA_CTRL 124 //0x01F0 // McBSP D/A FIFO Control
#define LAS0_FIFO_ADDR_MODE 125 //0x01F4 // FIFO Addressing Mode Select
//
// LAS1 Read Function Write Function
// -----------------------------------------------------------------
#define LAS1_ADC_FIFO 0 //0x0000 // Read A/D FIFO (16bit) -
#define LAS1_HDIO_FIFO 1 //0x0004 // Read High Speed Digital Input FIFO (16bit) -
#define LAS1_DAC1_FIFO 2 //0x0008 // - Write D/A1 FIFO (16bit)
#define LAS1_DAC2_FIFO 3 //0x000C // - Write D/A2 FIFO (16bit)
//*************************************************************************
// Register constants
//*************************************************************************
//
// Board Timers/Counters (for Set8254xxxx, Get82548254_xxxx, etc.)
//
#define TC_PCLK 0 // Pacer Clock 0
#define TC_BCLK 2 // Burst Clock
#define TC_ADC_SCNT 3 // A/D Sample counter
#define TC_DAC1_UCNT 4 // D/A1 Update counter
#define TC_DAC2_UCNT 5 // D/A2 Update counter
#define TC_DCNT 6 // Delay Counter
#define TC_ACNT 7 // About Counter
#define TC_DAC_CLK 8 // DAC clock
#define TC_UTC0 9 // 8254 TC Counter 0 User TC 0
#define TC_UTC1 10 // 8254 TC Counter 1 User TC 1
#define TC_UTC2 11 // 8254 TC Counter 2 User TC 2
//
// FIFO Status Word Bits (GetFifoStatus7520)
//
#define FS_DAC1_EMPTY 0x0001 // D0 - DAC1 FIFO not empty
#define FS_DAC1_HEMPTY 0x0002 // D1 - DAC1 FIFO not half empty
#define FS_DAC1_FULL 0x0004 // D2 - DAC1 FIFO not full
#define FS_DAC2_EMPTY 0x0010 // D4 - DAC2 FIFO not empty
#define FS_DAC2_HEMPTY 0x0020 // D5 - DAC2 FIFO not half empty
#define FS_DAC2_FULL 0x0040 // D6 - DAC2 FIFO not full
#define FS_ADC_EMPTY 0x0100 // D8 - ADC FIFO not empty
#define FS_ADC_HEMPTY 0x0200 // D9 - ADC FIFO not half empty
#define FS_ADC_FULL 0x0400 // D10 - ADC FIFO not full
#define FS_DIN_EMPTY 0x1000 // D12 - DIN FIFO not empty
#define FS_DIN_HEMPTY 0x2000 // D13 - DIN FIFO not half empty
#define FS_DIN_FULL 0x4000 // D14 - DIN FIFO not full
//
// Timer Status Word Bits (GetTimerStatus7520)
//
#define TS_PCLK_GATE 0x0001 // D0 - Pacer Clock Gate [0 - gated, 1 - enabled]
#define TS_BCLK_GATE 0x0002 // D1 - Burst Clock Gate [0 - disabled, 1 - running]
#define TS_DCNT_GATE 0x0004 // D2 - Pacer Clock Delayed Start Trigger [0 - delay over, 1 - delay in progress]
#define TS_ACNT_GATE 0x0008 // D3 - Pacer Clock About Trigger [0 - completed, 1 - in progress]
#define TS_PCLK_RUN 0x0010 // D4 - Pacer Clock Shutdown Flag [0 - Pacer Clock cannot be start triggered only by Software Pacer Start Command, 1 - Pacer Clock can be start triggered]
//
// SyncBus 0 Source Select (SetSbus0Source7520)
//
#define SBUS0_START_ADC_COMMAND 0x0 // Software A/D Start
#define SBUS0_PCLK 0x1 // Pacer Clock (Ext. Int. seeFunc.509)
#define SBUS0_BCLK 0x2 // Burst Clock
#define SBUS0_CGT_DAC1_UPDATE 0x3 // CGT controlled D/A1 Update
#define SBUS0_ETRG 0x4 // External Trigger
#define SBUS0_START_DACS_COMMAND 0x5 // Software Simultaneous D/A1 and D/A2 Update
#define SBUS0_DAC_CLK 0x6 // D/A Clock
#define SBUS0_UTC2 0x7 // User TC2 out
//
// SyncBus 1 Source Select (SetSbus1Source7520)
//
#define SBUS1_START_ADC_COMMAND 0x0 // Software A/D Start
#define SBUS1_PCLK 0x1 // Pacer Clock (Ext. Int. seeFunc.509)
#define SBUS1_BCLK 0x2 // Burst Clock
#define SBUS1_CGT_DAC2_UPDATE 0x3 // CGT controlled D/A2 Update
#define SBUS1_ETRG 0x4 // External Trigger
#define SBUS1_START_DACS_COMMAND 0x5 // Software Simultaneous D/A1 and D/A2 Update
#define SBUS1_DAC_CLK 0x6 // D/A Clock
#define SBUS1_UTC2 0x7 // User TC2 out
//
// SyncBus 2 Source Select (SetSbus2Source7520)
//
#define SBUS2_START_ADC_COMMAND 0x0 // Software A/D Start
#define SBUS2_START_PCLK_COMMAND 0x1 // Software Pacer Start
#define SBUS2_STOP_PCLK_COMMAND 0x2 // Software Pacer Stop
#define SBUS2_UPDATE_DAC1_COMMAND 0x3 // Software D/A1 Update
#define SBUS2_UPDATE_DAC2_COMMAND 0x4 // Software D/A2 Update
#define SBUS2_EPCLK 0x5 // External Pacer Clock
#define SBUS2_ETRG 0x6 // External Trigger
#define SBUS2_UTC2 0x7 // User TC2 out
//
// External Trigger polarity select (SetEtrgPolarity7520)
//
#define ETRG_POL_POSITIVE 0x0 // positive edge
#define ETRG_POL_NEGATIVE 0x1 // negative edge
//
// External Interrupt polarity select
//
#define EINT_POL_POSITIVE 0x0 // positive edge
#define EINT_POL_NEGATIVE 0x1 // negative edge
//
// User Output Signal select (SetUout0Source7520, SetUout1Source7520)
//
#define UOUT_ADC 0x0 // A/D Conversion Signal
#define UOUT_DAC1 0x1 // D/A1 Update
#define UOUT_DAC2 0x2 // D/A2 Update
#define UOUT_SOFTWARE 0x3 // Software Programmable
//
// Pacer clock select (SetPacerSource7520)
//
#define PCLK_INTERNAL 1 // Internal Pacer Clock
#define PCLK_EXTERNAL 0 // External Pacer Clock
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