dm7520_driver.h

rt 7520采集卡 linux驱动源代码

/*
	FILE NAME: dm7520_driver.h

	FILE DESCRIPTION: Definitions for the DM7520 driver

	PROJECT NAME: Linux DM7520 Driver, Library, and Example Programs

	PROJECT VERSION: (Defined in README.TXT)

	Copyright 2004 RTD Embedded Technologies, Inc.  All Rights Reserved.
*/

#ifndef DM7520_DRIVER_H
#define DM7520_DRIVER_H

#include <linux/kernel.h>

/* For character devices */
#include <linux/time.h>
#include <linux/fs.h>
#include <linux/wrapper.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <linux/proc_fs.h>

#include "dm7520.h"
#include "dm7520_reg.h"

#ifndef KERNEL_VERSION
#define KERNEL_VERSION(a,b,c) ((a)*65536+(b)*256+(c))
#endif

#if LINUX_VERSION_CODE > KERNEL_VERSION(2,2,0)
#include <asm/uaccess.h>  /* put_user */
#endif

/*
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)
typedef  struct wait_queue *wait_queue_head_t;
#endif
*/

#ifndef DECLARE_WAIT_QUEUE_HEAD
#define DECLARE_WAIT_QUEUE_HEAD(head) struct wait_queue *head = NULL
typedef  struct wait_queue *wait_queue_head_t;
#define init_waitqueue_head(head) (*(head)) = NULL
#endif

#define SUCCESS 0

#define DEVICE_NAME "rtd-dm7520"
//#define DEFDMABUFSIZE  8192 /* fifosize*samplesize */
//#define DMABUFSIZE  DEFDMABUFSIZE

#define MAXFIFOSIZE 32*1024

#define MAXDM7520 4

typedef struct {
	time_t start;
	time_t end;
	int timeout;
} dm7520Timer;

typedef struct {
                char dmainuse;     // is DMA channel in use?
				char direction;
				uint32_t dmamode;
				uint32_t dmaladdr; // local (board side) DMA address
				unsigned char * dmabuf;
				unsigned char * dmatempbuf;
				unsigned char * userBuffer;         //used for writing DMA
				uint32_t tempBufOffset;		//used for writing DMA
				uint32_t tempBufSize;		//used for writing DMA
                char usedby;        // which read/write source uses it?
				
               } dm7520_dmastruct;

typedef struct {
                unsigned int lcr_mmba;
                unsigned int lcr_ioba;
                unsigned int las0;
                unsigned int las1;
                volatile uint32_t * lasmap[LASMAX];
                int fifosize;
                uint32_t jiffie_r;
                uint32_t jiffie_w;
                char irq;
                char opened;
                char present;
                char flags;
				char devname[33];
				char readchan;
				char writechan;
                int errcode;
				struct fasync_struct *async_queue; /* Async notification*/
				wait_queue_head_t inq;             /* POLL queue */
				wait_queue_head_t outq;            /* POLL queue */
  				wait_queue_head_t readq;           /* Blocking read queue */
  				wait_queue_head_t writeq;          /* Blocking write queue */
                
				dm7520_dmastruct dmasetup[2];
				unsigned char * control;
				char *mmap_buf;
				long mmap_size;
				struct proc_dir_entry *procfile;
               } DM7520_STAT;

extern DM7520_STAT dm7520_table[MAXDM7520];

#define READ_TIMEOUT_SHORT 5
#define WRITE_TIMEOUT_SHORT 5
#define READ_TIMEOUT_LONG 20
#define WRITE_TIMEOUT_LONG 20

#define DM7520_FLAGS_BMCAP	0x01
#define DM7520_FLAGS_BMMOD	0x02
#define DM7520_FLAGS_FIFO8  0x04

#define DM7520_LAS0_LENGTH 512
#define DM7520_LAS1_LENGTH 16
#define DM7520_LCFG_LENGTH 0x100

/* put 32bit value "data" to board "b", address space "las", "port"th register*/
#define PUTMEM32(b,las,port,data)    *(dm7520_table[(b)].lasmap[(las)]+(port))=(uint32_t)(data)
/* read 32bit value from board "b", address space "las", "port"th register*/
#define GETMEM32(b,las,port)         *(dm7520_table[(b)].lasmap[(las)]+(port))


#define DA1_FIFONF (0!=(GETMEM32(devminor,LAS0,LAS0_ADC)& FS_DAC1_FULL))
#define DA2_FIFONF (0!=(GETMEM32(devminor,LAS0,LAS0_ADC)& FS_DAC2_FULL))

#define DA1_FIFONE (0!=(GETMEM32(devminor,LAS0,LAS0_ADC)& FS_DAC1_EMPTY))
#define DA2_FIFONE (0!=(GETMEM32(devminor,LAS0,LAS0_ADC)& FS_DAC2_EMPTY))

#define AD_FIFONF (0!=(GETMEM32(devminor,LAS0,LAS0_ADC)& FS_ADC_FULL))
#define HD_FIFONF (0!=(GETMEM32(devminor,LAS0,LAS0_ADC)& FS_DIN_FULL))

#define ADC_FIFONE (0!=(GETMEM32(devminor,LAS0,LAS0_ADC)& FS_ADC_EMPTY))
#define HDIN_FIFONE (0!=(GETMEM32(devminor,LAS0,LAS0_ADC)& FS_DIN_EMPTY))

#define DMABUF(b,ch)			(dm7520_table[(b)].dmasetup[(ch)].dmabuf)
#define DMASIZE(b)				(dm7520_table[(b)].fifosize)
#define DMATEMPBUF(b,ch)			(dm7520_table[(b)].dmasetup[(ch)].dmatempbuf)
#define TEMPBUFFLAG(b,ch,bi) (*(dm7520_table[(b)].control+bi+ch*CONTROLFLAGSIZE))

#define CONTROLBUF(b)		(dm7520_table[(b)].control)

#define USEDTEMPBUFSIZE(b,ch)        (dm7520_table[(b)].dmasetup[(ch)].tempBufSize)
#define TEMPBUFOFFSET(b,ch)        (dm7520_table[(b)].dmasetup[(ch)].tempBufOffset)
#define USERBUF(b,ch)        		(dm7520_table[(b)].dmasetup[(ch)].userBuffer)

/* put 16bit value "data" to board "b", address space "las", "port"th register*/
#define PUTMEM16(b,las,port,data)    *((uint16_t*)(dm7520_table[(b)].lasmap[(las)]+(port)))=(uint16_t)(data)
/* read 16bit value from board "b", address space "las", "port"th register*/
#define GETMEM16(b,las,port)         (uint16_t)*((uint16_t*)(dm7520_table[(b)].lasmap[(las)]+(port)))

//
// LCFG: PLX 9080 local config & runtime registers
//
#define LCFG_ITCSR              26 //0x0068    // INTCSR, Interrupt Control/Status Register
#define LCFG_DMAMODE0           32 //0x0080    // DMA Channel 0 Mode Register
#define LCFG_DMAPADR0           33 //0x0084    // DMA Channel 0 PCI Address Register
#define LCFG_DMALADR0           34 //0x0088    // DMA Channel 0 Local Address Register
#define LCFG_DMASIZ0            35 //0x008C    // DMA Channel 0 Transfer Size (Bytes) Register
#define LCFG_DMADPR0            36 //0x0090    // DMA Channel 0 Descriptor Pointer Register
#define LCFG_DMAMODE1           37 //0x0094    // DMA Channel 1 Mode Registe
#define LCFG_DMAPADR1           38 //0x0098    // DMA Channel 1 PCI Address Register
#define LCFG_DMALADR1           39 //0x009C    // DMA Channel 1 Local Address Register
#define LCFG_DMASIZ1            40 //0x00A0    // DMA Channel 1 Transfer Size (Bytes) Register
#define LCFG_DMADPR1            41 //0x00A4    // DMA Channel 1 Descriptor Pointer Register
#define LCFG_DMACSR             42 //0x00A8,A9 // DMA Channel 0&1 Command/Status Register
#define LCFG_DMAARB             43 //0x00AC    // DMA Arbitration Register
#define LCFG_DMATHR             44 //0x00B0    // DMA Threshold Register

#define LCFG_PCILTR              3 //0x000C    // -


#define NO_ARG 0                // Value for dummy writes to control registers

//
// DMA Channel 0 Command/Status bits
//
#define DMA0_ENABLED      0x01   // DMA Channel 0 enabled
#define DMA0_START        0x02   // DMA Channel 0 started
#define DMA0_ABORT        0x04   // Abort DMA Channel 0 transfer
#define DMA0_CLEAR_IT     0x08   // Clear DMA Channel 0 IT
#define DMA0_DONE         0x10   // DMA Channel 0 transfer done

//
// DMA Channel 1 Command/Status bits
//
#define DMA1_ENABLED      0x01   // DMA Channel 0 enabled
#define DMA1_START        0x02   // DMA Channel 0 started
#define DMA1_ABORT        0x04   // Abort DMA Channel 0 transfer
#define DMA1_CLEAR_IT     0x08   // Clear DMA Channel 0 IT
#define DMA1_DONE         0x10   // DMA Channel 1 transfer done

//
// DMA Channel 0 Command/Status bits
//
#define DMAM0_8BIT         0x0000       //0x0000    8 bit wide transfer
#define DMAM0_16BIT        BIT_00       //0x0001    16 bit wide transfer
#define DMAM0_32BIT        BIT_00|BIT_01//0x0003    32 bit wide transfer
#define DMAM0_RDYEN        BIT_06       //0x0040    READY enable
#define DMAM0_BTERM        BIT_07       //0x0080    BTERM enable
#define DMAM0_LBURST       BIT_08       //0x0100    Local Burst enable
#define DMAM0_CHAIN        BIT_09       //0x0200    Chain mode DMA
#define DMAM0_ITEN         BIT_10       //0x0400    DMA done IT enable
#define DMAM0_LA_CONST     BIT_11       //0x0800    Local Address constant
#define DMAM0_DEMAND       BIT_12       //0x1000    Demand mode DMA
#define DMAM0_WRANDI       BIT_13       //0x2000    Write and Invalidate mode DMA
#define DMAM0_CLRCNT       BIT_16       //0x010000  Clear transfer count
#define DMAM0_IT_PCI       BIT_17       //0x020000  DMA IT rerouted to PCI IT

//
// DMA Channel 1 Command/Status bits
//
#define DMAM1_8BIT         0x0000       //0x0000    8 bit wide transfer
#define DMAM1_16BIT        BIT_00       //0x0001    16 bit wide transfer
#define DMAM1_32BIT        BIT_00|BIT_01//0x0003    32 bit wide transfer
#define DMAM1_RDYEN        BIT_06       //0x0040    READY enable
#define DMAM1_BTERM        BIT_07       //0x0080    BTERM enable
#define DMAM1_LBURST       BIT_08       //0x0100    Local Burst enable
#define DMAM1_CHAIN        BIT_09       //0x0200    Chain mode DMA
#define DMAM1_ITEN         BIT_10       //0x0400    DMA done IT enable
#define DMAM1_LA_CONST     BIT_11       //0x0800    Local Address constant
#define DMAM1_DEMAND       BIT_12       //0x1000    Demand mode DMA
#define DMAM1_WRANDI       BIT_13       //0x2000    Write and Invalidate mode DMA
#define DMAM1_CLRCNT       BIT_16       //0x010000  Clear transfer count
#define DMAM1_IT_PCI       BIT_17       //0x020000  DMA IT rerouted to PCI IT

//
// DMA Mode Setups
//
#define DMAMODE0_NORMAL    DMAM0_IT_PCI|DMAM0_16BIT|DMAM0_LA_CONST|DMAM0_RDYEN|DMAM0_LBURST
#define DMAMODE0_DEMAND    DMAMODE0_NORMAL|DMAM0_DEMAND
#define DMAMODE0_NORMAL_CHAIN    DMAMODE0_NORMAL|DMAM0_CHAIN
#define DMAMODE0_DEMAND_CHAIN    DMAMODE0_DEMAND|DMAM0_CHAIN

#define DMAMODE1_NORMAL    DMAM1_IT_PCI|DMAM1_16BIT|DMAM1_LA_CONST|DMAM1_RDYEN|DMAM1_LBURST
#define DMAMODE1_DEMAND    DMAMODE1_NORMAL|DMAM1_DEMAND
#define DMAMODE1_NORMAL_CHAIN    DMAMODE1_NORMAL|DMAM1_CHAIN
#define DMAMODE1_DEMAND_CHAIN    DMAMODE1_DEMAND|DMAM1_CHAIN

//
// DMA Transfer Direction
//
#define DMAD_FROMCARD      1            // DMA transfer from card to memory
#define DMAD_TOCARD        0            // DMA transfer from memory to card

//
// Chained DMA Transfer Direction
//
#define CHAINED_READ       8            // DMA transfer from memory to card
#define CHAINED_WRITE      0            // DMA transfer from card to memory

//
// DMA Local Addresses   (0x40000000+LAS1 offset)
//
#define DMALADDR_ADC       0x40000000   // A/D FIFO
#define DMALADDR_HDIN      0x40000004   // High Speed Digital Input FIFO
#define DMALADDR_DAC1      0x40000008   // D/A1 FIFO
#define DMALADDR_DAC2      0x4000000C   // D/A2 FIFO

//
// PLX IT enable masks
//
#define PIRQE_PCI         BIT_08 //0x00000100       //PCI Interrupt Enable (default=on)
#define PIRQE_LINT        BIT_11 //0x00000800       //Local Interrupt Enable
#define PIRQE_DMA0        BIT_18 //0x00040000       //DMA Channel 0 Interrupt Enable
#define PIRQE_DMA1        BIT_19 //0x00080000       //DMA Channel 1 Interrupt Enable

//
// PLX IT status masks
//
#define PIRQS_LINT        BIT_15 //0x00008000       //Local Interrupt Active
#define PIRQS_DMA0        BIT_21 //0x00200000       //DMA Channel 0 Interrupt Active
#define PIRQS_DMA1        BIT_22 //0x00400000       //DMA Channel 1 Interrupt Active

// End internal constant definitions

extern void dm7520_incuse(void);
extern void dm7520_decuse(void);

#endif /*DM7520_DRIVER_H*/