📄 dm6430ioctl.h
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/* FILE NAME: dm6430ioctl.h FILE DESCRIPTION: This header file defines the driver ioctl interface PROJECT NAME: Linux DM6430 Driver, Library, and Example Programs PROJECT VERSION: (Defined in README.TXT) Copyright 2004 RTD Embedded Technologies, Inc. All Rights Reserved.*/#ifndef __dm6430ioctl__h_#define __dm6430ioctl__h_#include <linux/ioctl.h>#include <linux/types.h>#ifdef __cplusplusextern "C" {#endif/* * Signal sender code */#define DM6430HR_SI_CODE SI_MESGQ/* * 8 megahertz clock frequency */#define DM6430HR_8MHZ 8000000/*******************************************************************************Board registers*******************************************************************************/enum DM6430HR_Regs { r_CLEAR_6430 = 0, // Clear Register (Read/Write) r_STATUS_6430 = 2, // Status Register (Read) r_CONTROL_6430 = 2, // Control Register (Write) r_AD_6430 = 4, // AD Data (Read) r_CHANNEL_GAIN_6430 = 4, // Channel/Gain Register (Write) r_AD_TABLE_6430 = 4, // AD Table (Write) r_DIGITAL_TABLE_6430 = 4, // Digital Table (Write) r_START_CONVERSION_6430 = 6, // Start Conversion (Read) r_TRIGGER_6430 = 6, // Trigger Register (Write) r_IRQ_6430 = 8, // IRQ Register (Write) r_DIN_FIFO_6430 = 10, // Digital Input FIFO Data (Read) r_DIN_CONFIG_6430 = 10, // Config Digital Input FIFO (Write) r_DAC1_6430 = 12, // DAC 1 Data (Write) r_LOAD_AD_SAMPLE_COUNT_6430 = 14, // Load A/D Sample Counter (Read) r_DAC2_6430 = 14, // DAC 2 Data (Write) r_TIMER_CLCK0_6430 = 16, // Timer/Counter 0 (Read/Write) r_TIMER_CLCK1_6430 = 18, // Timer/Counter 1 (Read/Write) r_TIMER_CLCK2_6430 = 20, // Timer/Counter 2 (Read/Write) r_TIMER_CTRL_6430 = 22, // Timer/Counter Control Word (Write) r_DIO_PORT_0_6430 = 24, // Digital I/O Port 0 Register r_DIO_PORT_1_6430 = 26, // Digital I/O Port 1 Register r_DIO_PORT_DIR_6430 = 28, // Digital I/O Port 0 Direction Register r_DIO_PORT_MASK_6430 = 28, // Digital I/O Port 0 Mask Register r_DIO_PORT_COMP_6430 = 28, // Digital I/O Port 0 Compare Register r_DIO_CLEAR_6430 = 28, // Digital I/O Clear Register r_DIO_STATUS_6430 = 30, // Digital I/O Status Register r_DIO_MODE_6430 = 30 // Digital I/O Mode Register};/*******************************************************************************Registers which support streaming read*******************************************************************************/enum DM6430HR_STR_Regs { rSTR_AD_6430 = r_AD_6430, // AD Data (Read) rSTR_DIN_FIFO_6430 = r_DIN_FIFO_6430 // Digital Input FIFO Data (Read) };/*******************************************************************************Streaming read transfer types*******************************************************************************/enum DM6430HR_STR_TYPE { DM6430HR_STR_TYPE_BYTE = 1, /* 8 bits */ DM6430HR_STR_TYPE_WORD /* 16 bits */};/* clear flags codes for r_CLEAR_6430 reg */enum DM6430HR_CF { DM6430_CL_BOARD = 0x0001, DM6430_CL_AD_FIFO = 0x0002, DM6430_CL_AD_DMA_DONE = 0x0004, DM6430_CL_CLEAR_GAIN = 0x0008, DM6430_CL_RESET_GAIN = 0x0010, DM6430_CL_DIO_FIFO = 0x0020, DM6430_CL_IRQ1 = 0x0040, DM6430_CL_IRQ2 = 0x0080,};/*******************************************************************************Bit masks used to access individual bits in Digital I/O Status Register*******************************************************************************//* * Mask to extract digital port 1 direction bit */#define DIO_STATUS_PORT1_DIRECTION 0x04/* * Mask to extract digital interrupt mode bit */#define DIO_STATUS_IRQ_MODE 0x08/* * Mask to extract digital interrupt enabled status bit */#define DIO_STATUS_IRQ_ENABLE 0x10/* * Mask to extract digital input sample clock source bit */#define DIO_STATUS_SAMPLE_CLOCK 0x20/* * Mask to extract digital interrupt status bit */#define DIO_STATUS_IRQ_STATUS 0x40/* * Mask to extract */#define DIO_STATUS_STROBE_STATUS 0x80/* struct for DM6430HR_IOCTL_INB/DM6430HR_IOCTL_OUTB */struct DM6430HR_IO8 { /* * Target register */ enum DM6430HR_Regs reg; /* * Value to write to register or value read from register */ u_int8_t value;};/* struct for DM6430HR_IOCTL_MOUTW */struct DM6430HR_MIO8 { /* * Target register */ enum DM6430HR_Regs reg; /* * Mask which controls which register bits are changeable */ u_int8_t mask; /* * Value to write to register */ u_int8_t value;};/* struct for DM6430HR_IOCTL_INW/DM6430HR_IOCTL_OUTW */struct DM6430HR_IO16 { /* * Target register */ enum DM6430HR_Regs reg; /* * Value to write to register or value read from register */ u_int16_t value;};/* struct for DM6430HR_IOCTL_MOUTW */struct DM6430HR_MIO16 { /* * Target register */ enum DM6430HR_Regs reg; /* * Mask which controls which register bits are changeable */ u_int16_t mask; /* * Value to write to register */ u_int16_t value;};/* timer counters of DM6430HR */enum DM6430HR_CLK { /* * Timer/Counter 0 */ DM6430HR_CLK0, /* * Timer/Counter 1 */ DM6430HR_CLK1, /* * Timer/Counter 2 */ DM6430HR_CLK2};/* DMA channels of DM6430HR */enum DM6430HR_DMA { /* * First DMA circuit on board */ DM6430HR_DMA1, /* * Second DMA circuit on board */ DM6430HR_DMA2};/* IRQ channels of DM6430HR */enum DM6430HR_INT { /* * First interrupt circuit on board */ DM6430HR_INT1, /* * Second interrupt circuit on board */ DM6430HR_INT2};/* Clock modes, r_TIMER_CTRL_6430 = BA + 22 */enum DM6430HR_CLK_MODE { /* * Event count */ DM6430HR_CLK_MODE0, /* * Programmable 1-shot */ DM6430HR_CLK_MODE1, /* * Rate generator */ DM6430HR_CLK_MODE2, /* * Square wave rate generator */ DM6430HR_CLK_MODE3, /* * Software triggered strobe */ DM6430HR_CLK_MODE4, /* * Hardware triggered strobe */ DM6430HR_CLK_MODE5};⌨️ 快捷键说明
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