librtd-dm6430.c

rt 6430 采集卡 linux下驱动源代码

}


int
ClearIRQ16430(int descriptor) {
    return ClearRegister6430(descriptor, DM6430_CL_IRQ2);
}


int
InitBoard6430(int descriptor) {
    if (ClearBoard6430(descriptor) == -1) {
	return -1;
    }
    if (ClearADDMADone6430(descriptor) == -1) {
	return -1;
    }
    if (ClearChannelGainTable6430(descriptor) == -1) {
	return -1;
    }
    return ClearADFIFO6430(descriptor);
}


int
EnableIRQ6430(int descriptor, enum DM6430HR_INT IRQChannel) {
    struct DM6430HR_IE	io_request = {IRQChannel, 1};

    return ioctl(descriptor, DM6430HR_IOCTL_IRQ_ENABLE, &io_request);
}


int
DisableIRQ6430(int descriptor, enum DM6430HR_INT IRQChannel) {
    struct DM6430HR_IE	io_request = {IRQChannel, 0};

    return ioctl(descriptor, DM6430HR_IOCTL_IRQ_ENABLE, &io_request);
}


int
GetIRQCounter6430(
    int descriptor,
    enum DM6430HR_INT IRQChannel,
    unsigned long *counter_value_p
) {
    int			status;
    struct DM6430HR_GIC	io_request = {IRQChannel, 0};

    status = ioctl(descriptor, DM6430HR_IOCTL_GET_IRQ_COUNTER, &io_request);
    if (status != -1) {
	*counter_value_p = io_request.counter;
    }
    return status;
}


int
InstallDMA6430(int descriptor, enum DM6430HR_DMA DMAChannel) {
    struct DM6430HR_DI	io_request = {DMAChannel, 1};

    return ioctl(descriptor, DM6430HR_IOCTL_DMA_INSTALL, &io_request);
}


int
DeInstallDMA6430(int descriptor, enum DM6430HR_DMA DMAChannel) {
    struct DM6430HR_DI	io_request = {DMAChannel, 0};

    return ioctl(descriptor, DM6430HR_IOCTL_DMA_INSTALL, &io_request);
}


int
GetDmaData6430(
    int descriptor,
    void *dma_buffer_p,
    enum DM6430HR_DMA DMAChannel,
    size_t length,
    size_t offset,
    size_t *bytes_transferred_p
) {
    int			status;
    struct DM6430HR_GDD	io_request =
	{DMAChannel, dma_buffer_p, length, offset};

    status = ioctl(descriptor, DM6430HR_IOCTL_DMA_GETDATA, &io_request);
    if (status != -1) {
	*bytes_transferred_p = io_request.length;
    }
    return status;
}


int
StartDMA6430(
    int descriptor,
    enum DM6430HR_DMA DMAChannel,
    size_t TransferBytes
) {
    struct DM6430HR_DST	io_request = {DMAChannel, TransferBytes};

    return ioctl(descriptor, DM6430HR_IOCTL_DMA_START, &io_request);
}

int
StopDMA6430(int descriptor, enum DM6430HR_DMA DMAChannel) {
    return ioctl(descriptor, DM6430HR_IOCTL_DMA_STOP, DMAChannel);
}


int
GetAutoincData6430(
    int descriptor,
    enum DM6430HR_STR_Regs from_register,
    enum DM6430HR_STR_TYPE type,
    void *buffer_p,
    size_t element_num
) {
    struct DM6430HR_GID	io_request =
	{from_register, type, buffer_p, element_num};

    return ioctl(descriptor, DM6430HR_IOCTL_DMA_GETINC, &io_request);
}


int
ReadStatus6430(int descriptor, u_int16_t *status_p) {
    return inw6430(descriptor, r_STATUS_6430, status_p);
}


int
IsADFIFOEmpty6430(int descriptor, int *ad_fifo_empty_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*ad_fifo_empty_p = !(status_register & 0x0001);
    }
    return status;
}


int
IsADFIFOFull6430(int descriptor, int *ad_fifo_full_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*ad_fifo_full_p = !(status_register & 0x0002);
    }
    return status;
}


int
IsADHalted6430(int descriptor, int *ad_halted_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*ad_halted_p = (status_register & 0x0004);
    }
    return status;
}


int
IsADConverting6430(int descriptor, int *ad_converting_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*ad_converting_p = !(status_register & 0x0008);
    }
    return status;
} 


int
IsADDMADone6430(int descriptor, int *ad_dma_done_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*ad_dma_done_p = (status_register & 0x0010);
    }
    return status;
} 


int
IsFirstADDMADone6430(int descriptor, int *ad_first_dma_done_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*ad_first_dma_done_p = (status_register & 0x0020);
    }
    return status;
} 


int
IsBurstClockOn6430(int descriptor, int *ad_burst_clock_on_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*ad_burst_clock_on_p = (status_register & 0x0040);
    }
    return status;
} 


int
IsPacerClockOn6430(int descriptor, int *ad_pacer_clock_on_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*ad_pacer_clock_on_p = (status_register & 0x0080);
    }
    return status;
}


int
IsAboutTrigger6430(int descriptor, int *ad_about_trigger_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*ad_about_trigger_p = (status_register & 0x0100);
    }
    return status;
}


int
IsDigitalIRQ6430(int descriptor, int *digital_interrupt_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*digital_interrupt_p = (status_register & 0x0200);
    }
    return status;
}


int
IsDINFIFOEmpty6430(int descriptor, int *digital_fifo_empty_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*digital_fifo_empty_p = !(status_register & 0x0400);
    }
    return status;
}


int
IsDINFIFOHalf6430(int descriptor, int *digital_fifo_half_full_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*digital_fifo_half_full_p = !(status_register & 0x0800);
    }
    return status;
}


int
IsDINFIFOFull6430(int descriptor, int *digital_fifo_full_p) {
    int		status;
    u_int16_t	status_register;

    status = ReadStatus6430(descriptor, &status_register);
    if (status != -1) {
	*digital_fifo_full_p = !(status_register & 0x1000);
    }
    return status;
}


int
LoadControlRegister6430(int descriptor, u_int16_t value) {
    return outw6430(descriptor, r_CONTROL_6430, value);
}


int
EnableTables6430(
    int descriptor,
    int Enable_AD_Table,
    int Enable_Digital_Table
) {
    u_int16_t		enable_mask = 0x0000;

    /*
     * Cannot enable digital table without enabling A/D table
     */

    if ((Enable_AD_Table == 0) && (Enable_Digital_Table != 0)) {
	errno = EOPNOTSUPP;
	return -1;
    }

    if (Enable_AD_Table != 0) {
	enable_mask |= (1 << 2);
    }

    if (Enable_Digital_Table != 0) {
	enable_mask |= (1 << 3);
    }

    return moutw6430(descriptor, r_CONTROL_6430, 0xFFF3, enable_mask);
}


int
ChannelGainDataStore6430(int descriptor, int Enable) {
    u_int16_t	enable_mask = 0x0000;

    if (Enable != 0) {
	enable_mask |= (1 << 4);
    }
    return moutw6430(descriptor, r_CONTROL_6430, 0xFFEF, enable_mask);
}


int
SelectTimerCounter6430(int descriptor, enum DM6430HR_CLK_SEL Select) {
    if (validate_clock_select(Select) == -1) {
	return -1;
    }

    return moutw6430(descriptor, r_CONTROL_6430, 0xFF9F, Select << 5);
}


int
SetSampleCounterStop6430(int descriptor, int Disable) {
    u_int16_t	disable_mask = 0x0000;

    if (Disable != 0) {
	disable_mask |= (1 << 7);
    }
    return moutw6430(descriptor, r_CONTROL_6430, 0xFF7F, disable_mask);
}


int
SetPauseEnable6430(int descriptor, int Enable) {
    u_int16_t	enable_mask = 0x0000;

    if (Enable != 0) {
	enable_mask |= (1 << 8);
    }

    return moutw6430(descriptor, r_CONTROL_6430, 0xFEFF, enable_mask);
}


int
ReadADData6430(int descriptor, int16_t *ad_data_p) {
    int		status;
    u_int16_t	ad_data;

    status = inw6430(descriptor, r_AD_6430, &ad_data);
    if (status != -1) {
	*ad_data_p = (int16_t) ad_data;
    }

    return status;
}


int
ReadChannelGainDataStore6430(int descriptor, u_int16_t *cgds_data_p) {
    return inw6430(descriptor, r_AD_6430, cgds_data_p);
}


int
SetChannelGain6430(
    int descriptor,
    enum DM6430HR_AIN Channel,
    enum DM6430HR_GAIN Gain,
    enum DM6430HR_SE Se_Diff
) {

    switch (Channel) {
	case DM6430HR_AIN1:
	case DM6430HR_AIN2:
	case DM6430HR_AIN3:
	case DM6430HR_AIN4:
	case DM6430HR_AIN5:
	case DM6430HR_AIN6:
	case DM6430HR_AIN7:
	case DM6430HR_AIN8:
	case DM6430HR_AIN9:
	case DM6430HR_AIN10:
	case DM6430HR_AIN11:
	case DM6430HR_AIN12:
	case DM6430HR_AIN13:
	case DM6430HR_AIN14:
	case DM6430HR_AIN15:
	case DM6430HR_AIN16:
	    break;

	default:
	    errno = EINVAL;
	    return -1;
	    break;
    }

    switch (Gain) {
	case DM6430HR_GAINx1:
	case DM6430HR_GAINx2:
	case DM6430HR_GAINx4:
	case DM6430HR_GAINx8:
	    break;

	default:
	    errno = EINVAL;
	    return -1;
	    break;
    }

    switch (Se_Diff) {
	case DM6430HR_SE_SE:
	case DM6430HR_SE_DIFF:
	    break;

	default:
	    errno = EINVAL;
	    return -1;
	    break;
    }

    return outw6430(
	descriptor,
	r_CHANNEL_GAIN_6430,
	((Channel & 0xF) | ((Gain & 0x7) << 4) | ((Se_Diff & 1) << 9))
    );
}


int
LoadADTable6430(int descriptor, u_int16_t ADEntries, ADTableRow *ADTable_p) {
    int	entry_num;
    int	status;

    if ((ADEntries == 0) || (ADEntries > 1024)) {
	errno = EINVAL;
	return -1;
    }

    if (moutw6430(descriptor, r_CONTROL_6430, 0xFFFC, 0x1) == -1) {
	return -1;
    }

    for (entry_num = 0; entry_num < ADEntries; entry_num++) {
	u_int16_t	ADEntry;

	ADEntry = (
	    (ADTable_p[entry_num].Channel & 0xF)
	    |
	    ((ADTable_p[entry_num].Gain & 0x7) << 4)
	    |
	    ((ADTable_p[entry_num].Se_Diff & 1) << 9)
	    |
	    ((ADTable_p[entry_num].Pause & 1) << 10)
	    |
	    ((ADTable_p[entry_num].Skip & 1) << 11)
	);

	status = outw6430(descriptor, r_AD_TABLE_6430, ADEntry);
	if (status == -1) {
	    (void) moutw6430(descriptor, r_CONTROL_6430, 0xFFFC, 0x0);
	    return -1;
	}
    } 

    return moutw6430(descriptor, r_CONTROL_6430, 0xFFFC, 0x0);
}


int
LoadDigitalTable6430(int descriptor, u_int16_t entries, u_int16_t *table_p) {
    int	entry_num;
    int	status;

    if ((entries == 0) || (entries > 1024)) {
	errno = EINVAL;
	return -1;
    }

    if (moutw6430(descriptor, r_CONTROL_6430, 0xFFFC, 0x2) == -1) {
	return -1;
    }

    for (entry_num = 0; entry_num < entries; entry_num++) {
	status = outw6430(descriptor, r_DIGITAL_TABLE_6430, table_p[entry_num]);
	if (status == -1) {
	    (void) moutw6430(descriptor, r_CONTROL_6430, 0xFFFC, 0x0);
	    return -1;
	}
    }

    return moutw6430(descriptor, r_CONTROL_6430, 0xFFFC, 0x0);
}


int
StartConversion6430(int descriptor) {
    u_int16_t	dummy;

    return inw6430(descriptor, r_START_CONVERSION_6430, &dummy);
}


int
LoadTriggerRegister6430(int descriptor, u_int16_t value) {
    return outw6430(descriptor, r_TRIGGER_6430, value);
}


int
SetConversionSelect6430(int descriptor, enum DM6430HR_CONV Select) {
    switch (Select) {
	case DM6430HR_CONV_SOFT_TRIGGER:
	case DM6430HR_CONV_PACER_CLOCK:
	case DM6430HR_CONV_BURST_CLOCK:
	case DM6430HR_CONV_DIGITAL_INT:
	    break;

	default:
	    errno = EINVAL;
	    return -1;
	    break;
    }

    return moutw6430(descriptor, r_TRIGGER_6430, 0xFFFC, Select);
}


int
SetStartTrigger6430(int descriptor, enum DM6430HR_START_TRIG Start_Trigger) {
    switch (Start_Trigger) {
	case DM6430HR_START_TRIG_SOFTWARE:
	case DM6430HR_START_TRIG_EXTERNAL:
	case DM6430HR_START_TRIG_DIGITAL_INT:
	case DM6430HR_START_TRIG_USER_TC1:
	case DM6430HR_START_TRIG_GATE:
	    break;

	case DM6430HR_START_TRIG_RES1:
	case DM6430HR_START_TRIG_RES2:
	case DM6430HR_START_TRIG_RES3:
	    errno = EOPNOTSUPP;
	    return -1;
	    break;

	default:
	    errno = EINVAL;
	    return -1;
	    break;
    }

    return moutw6430(descriptor, r_TRIGGER_6430, 0xFFE3, Start_Trigger << 2);
}


int
SetStopTrigger6430(int descriptor, enum DM6430HR_STOP_TRIG Stop_Trigger) {
    switch (Stop_Trigger) {
	case DM6430HR_STOP_TRIG_SOFTWARE:
	case DM6430HR_STOP_TRIG_EXTERNAL:
	case DM6430HR_STOP_TRIG_DIGITAL_INT:
	case DM6430HR_STOP_TRIG_SAMPLE_CNT:
	case DM6430HR_STOP_TRIG_ABOUT_SOFTWARE:
	case DM6430HR_STOP_TRIG_ABOUT_EXTERNAL:
	case DM6430HR_STOP_TRIG_ABOUT_DIGITAL:
	case DM6430HR_STOP_TRIG_ABOUT_USER_TC1:
	    break;

	default:
	    errno = EINVAL;
	    return -1;
	    break;
    }

    return moutw6430(descriptor, r_TRIGGER_6430, 0xFF1F, Stop_Trigger << 5);
}


int
SetPacerClockSource6430(int descriptor, enum DM6430HR_PACER_CLK Source) {
    switch (Source) {
	case DM6430HR_PACER_CLK_INTERNAL:
	case DM6430HR_PACER_CLK_EXTERNAL:
	    break;

	default:
	    errno = EINVAL;
	    return -1;
	    break;
    }

    return moutw6430(descriptor, r_TRIGGER_6430, 0xFDFF, Source << 9);
}


int
SetBurstTrigger6430(int descriptor, enum DM6430HR_BURST_TRIG Burst_Trigger) {
    switch (Burst_Trigger) {
	case DM6430HR_BURST_TRIG_SOFTWARE:
	case DM6430HR_BURST_TRIG_PACER:
	case DM6430HR_BURST_TRIG_EXTERNAL:
	case DM6430HR_BURST_TRIG_DIGITAL:
	    break;

	default:
	    errno = EINVAL;
	    return -1;