ej_bbs.h.bak
来自「ADI blackfin DSP的基于device friver的jpeg压缩算」· BAK 代码 · 共 381 行
BAK
381 行
#ifndef EJ_BBS_H
#define EJ_BBS_H
/*********************************************************************
Include files
*********************************************************************/
#include <services\services.h> // system services
#include <drivers\adi_dev.h> // device manager includes
#include <drivers\ppi\adi_ppi.h> // PPI driver includes
#include "adi_itu656.h" // ITU656 utilities
#include "error_def.h"
#include "basic_type.h"
/*********************************************************************
ADSP-BF533/537 have only 1 PPI called PPI0
ADSP-BF561 has 2, PPI0 connected to video decoder, PPI1 to video encoder
*********************************************************************/
#if defined(__ADSPBF561__)
#define ENCODER_PPI (1)
#define DECODER_PPI (0)
#else
#define ENCODER_PPI (0)
#define DECODER_PPI (0)
#endif
/*********************************************************************
Processor Specifics
*********************************************************************/
/********************
Edinburgh 531-533
********************/
#if defined(__ADSP_EDINBURGH__) // Edinburgh class devices
typedef enum {
DEV_PPI,
DEV_SPORT0,
DEV_SPORT1,
DEV_SPI,
DEV_UART,
}DEV_TYPE_ID;
typedef enum { // DMA Channel ID
DMA_PPI, // DMA 0 - default channel for PPI.
DMA_SPORT0_RX, // DMA 1 - default channel for SPORT0 receive.
DMA_SPORT0_TX, // DMA 2 - default channel for SPORT0 transmit.
DMA_SPORT1_RX, // DMA 3 - default channel for SPORT1 receive.
DMA_SPORT1_TX, // DMA 4 - default channel for SPORT1 transmit
DMA_SPI, // DMA 5 - default channel for SPI.
DMA_UART_RX, // DMA 6 - default channel for UART receive.
DMA_UART_TX, // DMA 7 - default channel for UART transmit.
DMA_MDMA_D0, // Memory DMA Stream 0 Destination.
DMA_MDMA_S0, // Memory DMA Stream 0 Source.
DMA_MDMA_D1, // Memory DMA Stream 1 Destination.
DMA_MDMA_S1, // Memory DMA Stream 1 Source.
DMA_CHANNEL_COUNT, // number of DMA channels
} DMA_TYPE_ID;
typedef enum { // Stream IDs for memory DMA
DMA_MDMA_0, // memory DMA stream 0
DMA_MDMA_1, // memory DMA stream 1
DMA_MEMORY_STREAM_COUNT, // number of memory DMA streams
} DMA_STREAM_ID;
#endif
/********************
Braemar 534-537
********************/
#if defined(__ADSP_BRAEMAR__) // Braemar class devices
typedef enum {
DEV_PPI,
DEV_ETHERNET,
DEV_SPORT0,
DEV_SPORT1,
DEV_SPI,
DEV_UART0,
DEV_UART1,
}DEV_TYPE_ID;
typedef enum { // DMA Channel ID
DMA_PPI, // DMA 0 - default channel for PPI.
DMA_ETHERNET_RX, // DMA 1 - default channel for Ethernet MAC receive.
DMA_ETHERNET_TX, // DMA 2 - default channel for Ethernet MAC transmit.
DMA_SPORT0_RX, // DMA 3 - default channel for SPORT0 receive.
DMA_SPORT0_TX, // DMA 4 - default channel for SPORT0 transmit.
DMA_SPORT1_RX, // DMA 5 - default channel for SPORT1 receive.
DMA_SPORT1_TX, // DMA 6 - default channel for SPORT1 transmit
DMA_SPI, // DMA 7 - default channel for SPI.
DMA_UART0_RX, // DMA 8 - default channel for UART0 receive.
DMA_UART0_TX, // DMA 9 - default channel for UART0 transmit.
DMA_UART1_RX, // DMA 10 - default channel for UART1 receive.
DMA_UART1_TX, // DMA 11 - default channel for UART1 transmit.
DMA_MDMA_D0, // Memory DMA Stream 0 Destination.
DMA_MDMA_S0, // Memory DMA Stream 0 Source.
DMA_MDMA_D1, // Memory DMA Stream 1 Destination.
DMA_MDMA_S1, // Memory DMA Stream 1 Source.
DMA_CHANNEL_COUNT, // number of DMA channels
} DMA_TYPE_ID;
typedef enum { // Stream IDs for memory DMA
DMA_MDMA_0, // memory DMA stream 0
DMA_MDMA_1, // memory DMA stream 1
DMA_MEMORY_STREAM_COUNT, // number of memory DMA streams
} DMA_STREAM_ID;
#endif
/********************
Teton-Lite 534-537
********************/
#if defined(__ADSP_TETON__) // Teton class devices
typedef enum {
DEV_PPI1,
DEV_PPI2,
DEV_SPORT0,
DEV_SPORT1,
DEV_SPI,
DEV_UART,
}DEV_TYPE_ID;
typedef enum { // DMA Channel ID
DMA_PPI1, // DMA1 Channel 0 - default channel for PPI1
DMA_PPI2, // DMA1 Channel 1 - default channel for PPI2
DMA_DMA1_2, // DMA1 Channel 2
DMA_DMA1_3, // DMA1 Channel 3
DMA_DMA1_4, // DMA1 Channel 4
DMA_DMA1_5, // DMA1 Channel 5
DMA_DMA1_6, // DMA1 Channel 6
DMA_DMA1_7, // DMA1 Channel 7
DMA_DMA1_8, // DMA1 Channel 8
DMA_DMA1_9, // DMA1 Channel 9
DMA_DMA1_10, // DMA1 Channel 10
DMA_DMA1_11, // DMA1 Channel 11
DMA_MDMA1_D0, // DMA1 Memory DMA Stream 0 Destination.
DMA_MDMA1_S0, // DMA1 Memory DMA Stream 0 Source.
DMA_MDMA1_D1, // DMA1 Memory DMA Stream 1 Destination.
DMA_MDMA1_S1, // DMA1 Memory DMA Stream 1 Source.
DMA_DMA2_SPORT0_RX, // DMA2 Channel 0 - default channel for SPORT0 RX
DMA_DMA2_SPORT0_TX, // DMA2 Channel 1 - default channel for SPORT0 TX
DMA_DMA2_SPORT1_RX, // DMA2 Channel 2 - default channel for SPORT1 RX
DMA_DMA2_SPORT1_TX, // DMA2 Channel 3 - default channel for SPORT1 TX
DMA_DMA2_SPI, // DMA2 Channel 4 - default channel for SPI
DMA_DMA2_UART_RX, // DMA2 Channel 5 - default channel for UART RX
DMA_DMA2_UART_TX, // DMA2 Channel 6 - default channel for UART TX
DMA_DMA2_7, // DMA2 Channel 7
DMA_DMA2_8, // DMA2 Channel 8
DMA_DMA2_9, // DMA2 Channel 9
DMA_DMA2_10, // DMA2 Channel 10
DMA_DMA2_11, // DMA2 Channel 11
DMA_MDMA2_D0, // DMA2 Memory DMA Stream 0 Destination.
DMA_MDMA2_S0, // DMA2 Memory DMA Stream 0 Source.
DMA_MDMA2_D1, // DMA2 Memory DMA Stream 1 Destination.
DMA_MDMA2_S1, // DMA2 Memory DMA Stream 1 Source.
DMA_IMDMA_D0, // IMDMA Stream 0 Destination.
DMA_IMDMA_S0, // IMDMA Stream 0 Source.
DMA_IMDMA_D1, // IMDMA Stream 1 Destination.
DMA_IMDMA_S1, // IMDMA Stream 1 Source.
DMA_CHANNEL_COUNT, // number of DMA channels
} DMA_TYPE_ID;
typedef enum { // Stream IDs for memory DMA
DMA_MDMA1_0, // memory DMA, controller 1, stream 0
DMA_MDMA1_1, // memory DMA, controller 1, stream 1
DMA_MDMA2_0, // memory DMA, controller 2, stream 0
DMA_MDMA2_1, // memory DMA, controller 2, stream 1
DMA_IMDMA_0, // internal memory DMA, stream 0
DMA_IMDMA_1, // internal memory DMA, stream 1
DMA_MEMORY_STREAM_COUNT, // number of memory DMA streams
} DMA_STREAM_ID;
#endif
typedef enum { // Buffer types
DEV_BUFFER_UNDEFINED, // undefined
DEV_1D, // 1 dimensional buffer
DEV_2D, // 2 dimensional buffer
DEV_CIRC, // circular buffer
DEV_SEQ_1D, // sequential 1 dimensional buffer
} DEV_BUFFER_TYPE;
class EJ_BBS
{
public:
EJ_BBS();
virtual ~EJ_BBS();
/* init_core
*
* Description:
* init the core system,including pll,sdram,timer, interrupt ...
* but network setting is leave to user, may be add in later
*
*
*/
void init_core(void);
/* init_system_service
*
* Description:
* init the system service provided by adi system service lib
* u8 *pMemoryForSysService:
* point to the memory block that system service need,
* size_t *MemorySizeUsed:
* memory size used by system service, MemorySizeUsed =
* (ADI_DMA_BASE_MEMORY + ADI_DMA_CHANNEL_MEMORY*DmaChannelNum)
* + (ADI_INT_SECONDARY_MEMORY * SecHandlerNum)
* + (ADI_DCB_QUEUE_SIZE + (ADI_DCB_ENTRY_SIZE)*DcbCallbackNum);
*
* note, if use mem DMA, always need 2 channels for a memory copy
*
* Return:
* EJ_ERR_NONE success
* !EJ_ERR_NONE fail
*/
RESULT init_system_service(u8 *pMemoryForSysService, size_t *MemorySizeUsed ,
const size_t DmaChannelNum, const size_t IntSecHandlerNum, const size_t DcbCallbackNum);
/* init_device_driver
*
* Description:
* init the device driver provided by adi device driver lib
* u8 *pMemoryForSysService:
* point to the memory block that device driver need,
* size_t *MemorySizeUsed
* memory size used by ddr, MemorySizeUsed = ADI_DEV_BASE_MEMORY + (ADI_DEV_DEVICE_MEMORY * DevNum)
*
* Return:
* EJ_ERR_NONE success
* !EJ_ERR_NONE fail
*/
RESULT init_device_driver(u8 *pMemoryForDDR, size_t *MemorySizeUsed , const size_t DevNum);
/* config_device
*
* Description:
* config the device indicated by devType, using the ADI_DEV_CMD_VALUE_PAIR structure.
* u16 devType:
* device type, all the candicate list in enum: DEV_TYPE_ID,
* ADI_DEV_CMD_VALUE_PAIR *configurationTable:
* ADI_DEV_CMD_VALUE_PAIR structure used to configure device.
*
* Return:
* EJ_ERR_NONE success
* !EJ_ERR_NONE fail
*/
RESULT config_device(u16 devType, ADI_DEV_CMD_VALUE_PAIR *configurationTable, ADI_DCB_CALLBACK_FN ClientCallback);
void set_dma_callback(u16 dma_type, ADI_DCB_CALLBACK_FN ClientCallback);
/* set_dev_buffer
*
* Description:
* when use a device to inbound/outbound data, caller must tell the device which kind buffer type he used, and provide the buffer structure.
* u16 devType:
* device type, all the candicate list in enum: DEV_TYPE_ID,
* ADI_DEV_BUFFER * devBuffer:
* ADI device driver provide 3 kind of data flow method( 3 buffer type), circular, chained and chained with loopback.
* ADI_DEV_BUFFER_TYPE BufferType:
* the buffer type used.
*
* Return:
* EJ_ERR_NONE success
* !EJ_ERR_NONE fail
*/
RESULT set_dev_buffer(u16 devType, ADI_DEV_BUFFER * devBuffer, ADI_DEV_BUFFER_TYPE BufferType);
/* set_dev_start
*
* Description:
* call this interface to start the data flow with the device specific
* u16 devType:
* device type, all the candicate list in enum: DEV_TYPE_ID,
*
* Return: none
*/
void set_dev_start(u16 devType);
/* set_dev_stop
*
* Description:
* call this interface to stop the data flow with the device specific
* u16 devType:
* device type, all the candicate list in enum: DEV_TYPE_ID,
*
* Return: none
*/
void set_dev_stop(u16 devType );
/* config_memdma
*
* Description:
* config the memory dma stream, this call will open 2 dma channel.
* ADI_DMA_STREAM_ID StreamID:
* stream id
*
* EJ_ERR_NONE success
* !EJ_ERR_NONE fail
*/
RESULT config_memdma(ADI_DMA_STREAM_ID StreamID);
/* start_memdma
*
* Description:
* start the memory dma transfer on stream, with the specific 2 ADI_DMA_2D_TRANSFER struct.
* and the ElementWidth and callback.
*
* NOTE:
* if the element strid (Xmodify) is different between pDest and pSrc, the ElementWidth should be 1.
* the memory dma is set to stop mode, when the current work unit completes, the DMA channel
* stops automatically, after signaling an interrupt(if selected)
* return:
* EJ_ERR_NONE success
* !EJ_ERR_NONE fail
*/
RESULT start_memdma(ADI_DMA_STREAM_ID StreamID, ADI_DMA_2D_TRANSFER *pDest, ADI_DMA_2D_TRANSFER *pSrc,
u32 ElementWidth , ADI_DCB_CALLBACK_FN ClientCallback);
int creat_alternate_heap(void* heap_base_addr, u32 heap_size);
void set_data_cache(void);
void set_instruction_cache(void);
private:
private:
// DMA Manager data (base memory + memory for 1 DMA channel)
void *m_pDMAMgrData;
// Deferred Callback Manager data (memory for 1 service plus 4 posted callbacks)
void *m_pDCBMgrData;
// Device Manager data (base memory + memory for 1 device)
void *m_pDevMgrData;
// storage for interrupt manager data
void *m_pIntMgrData;
//handles
ADI_DCB_HANDLE m_DCBManagerHandle;
ADI_DMA_MANAGER_HANDLE m_DMAManagerHandle; // handle to the DMA Manager
ADI_DEV_MANAGER_HANDLE m_DeviceManagerHandle; // handle to the Device Manager
ADI_DEV_DEVICE_HANDLE m_ppiDeviceHandle; // handle to the device driver
// ADI_DEV_BUFFER * m_devBuffer;
ADI_DMA_STREAM_HANDLE m_mdmaHandle0;
ADI_DMA_STREAM_HANDLE m_mdmaHandle1;
// heap userid
u16 m_userid;
};
#endif
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