ej_bbs.h
来自「ADI blackfin DSP的基于device friver的jpeg压缩算」· C头文件 代码 · 共 419 行 · 第 1/2 页
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#ifndef EJ_BBS_H
#define EJ_BBS_H
/*********************************************************************
Include files
*********************************************************************/
#include <services\services.h> // system services
#include <drivers\adi_dev.h> // device manager includes
#include <drivers\ppi\adi_ppi.h> // PPI driver includes
#include "adi_itu656.h" // ITU656 utilities
#include "error_def.h"
#include "basic_type.h"
/*********************************************************************
ADSP-BF533/537 have only 1 PPI called PPI0
ADSP-BF561 has 2, PPI0 connected to video decoder, PPI1 to video encoder
*********************************************************************/
#if defined(__ADSPBF561__)
#define ENCODER_PPI (1)
#define DECODER_PPI (0)
#else
#define ENCODER_PPI (0)
#define DECODER_PPI (0)
#endif
/*********************************************************************
Processor Specifics
*********************************************************************/
/********************
Edinburgh 531-533
********************/
#if defined(__ADSP_EDINBURGH__) // Edinburgh class devices
typedef enum {
DEV_PPI,
DEV_SPORT0,
DEV_SPORT1,
DEV_SPI,
DEV_UART,
}DEV_TYPE_ID;
typedef enum { // DMA Channel ID
DMA_PPI, // DMA 0 - default channel for PPI.
DMA_SPORT0_RX, // DMA 1 - default channel for SPORT0 receive.
DMA_SPORT0_TX, // DMA 2 - default channel for SPORT0 transmit.
DMA_SPORT1_RX, // DMA 3 - default channel for SPORT1 receive.
DMA_SPORT1_TX, // DMA 4 - default channel for SPORT1 transmit
DMA_SPI, // DMA 5 - default channel for SPI.
DMA_UART_RX, // DMA 6 - default channel for UART receive.
DMA_UART_TX, // DMA 7 - default channel for UART transmit.
DMA_MDMA_D0, // Memory DMA Stream 0 Destination.
DMA_MDMA_S0, // Memory DMA Stream 0 Source.
DMA_MDMA_D1, // Memory DMA Stream 1 Destination.
DMA_MDMA_S1, // Memory DMA Stream 1 Source.
DMA_CHANNEL_COUNT, // number of DMA channels
} DMA_TYPE_ID;
typedef enum { // Stream IDs for memory DMA
DMA_MDMA_0, // memory DMA stream 0
DMA_MDMA_1, // memory DMA stream 1
DMA_MEMORY_STREAM_COUNT, // number of memory DMA streams
} DMA_STREAM_ID;
#endif
/********************
Braemar 534-537
********************/
#if defined(__ADSP_BRAEMAR__) // Braemar class devices
typedef enum {
DEV_PPI,
DEV_ETHERNET,
DEV_SPORT0,
DEV_SPORT1,
DEV_SPI,
DEV_UART0,
DEV_UART1,
}DEV_TYPE_ID;
typedef enum { // DMA Channel ID
DMA_PPI, // DMA 0 - default channel for PPI.
DMA_ETHERNET_RX, // DMA 1 - default channel for Ethernet MAC receive.
DMA_ETHERNET_TX, // DMA 2 - default channel for Ethernet MAC transmit.
DMA_SPORT0_RX, // DMA 3 - default channel for SPORT0 receive.
DMA_SPORT0_TX, // DMA 4 - default channel for SPORT0 transmit.
DMA_SPORT1_RX, // DMA 5 - default channel for SPORT1 receive.
DMA_SPORT1_TX, // DMA 6 - default channel for SPORT1 transmit
DMA_SPI, // DMA 7 - default channel for SPI.
DMA_UART0_RX, // DMA 8 - default channel for UART0 receive.
DMA_UART0_TX, // DMA 9 - default channel for UART0 transmit.
DMA_UART1_RX, // DMA 10 - default channel for UART1 receive.
DMA_UART1_TX, // DMA 11 - default channel for UART1 transmit.
DMA_MDMA_D0, // Memory DMA Stream 0 Destination.
DMA_MDMA_S0, // Memory DMA Stream 0 Source.
DMA_MDMA_D1, // Memory DMA Stream 1 Destination.
DMA_MDMA_S1, // Memory DMA Stream 1 Source.
DMA_CHANNEL_COUNT, // number of DMA channels
} DMA_TYPE_ID;
typedef enum { // Stream IDs for memory DMA
DMA_MDMA_0, // memory DMA stream 0
DMA_MDMA_1, // memory DMA stream 1
DMA_MEMORY_STREAM_COUNT, // number of memory DMA streams
} DMA_STREAM_ID;
#endif
/********************
Teton-Lite 561
********************/
#if defined(__ADSP_TETON__) // Teton class devices
typedef enum {
DEV_PPI1,
DEV_PPI2,
DEV_SPORT0,
DEV_SPORT1,
DEV_SPI,
DEV_UART,
}DEV_TYPE_ID;
typedef enum { // DMA Channel ID
DMA_PPI1, // DMA1 Channel 0 - default channel for PPI1
DMA_PPI2, // DMA1 Channel 1 - default channel for PPI2
DMA_DMA1_2, // DMA1 Channel 2
DMA_DMA1_3, // DMA1 Channel 3
DMA_DMA1_4, // DMA1 Channel 4
DMA_DMA1_5, // DMA1 Channel 5
DMA_DMA1_6, // DMA1 Channel 6
DMA_DMA1_7, // DMA1 Channel 7
DMA_DMA1_8, // DMA1 Channel 8
DMA_DMA1_9, // DMA1 Channel 9
DMA_DMA1_10, // DMA1 Channel 10
DMA_DMA1_11, // DMA1 Channel 11
DMA_MDMA1_D0, // DMA1 Memory DMA Stream 0 Destination.
DMA_MDMA1_S0, // DMA1 Memory DMA Stream 0 Source.
DMA_MDMA1_D1, // DMA1 Memory DMA Stream 1 Destination.
DMA_MDMA1_S1, // DMA1 Memory DMA Stream 1 Source.
DMA_DMA2_SPORT0_RX, // DMA2 Channel 0 - default channel for SPORT0 RX
DMA_DMA2_SPORT0_TX, // DMA2 Channel 1 - default channel for SPORT0 TX
DMA_DMA2_SPORT1_RX, // DMA2 Channel 2 - default channel for SPORT1 RX
DMA_DMA2_SPORT1_TX, // DMA2 Channel 3 - default channel for SPORT1 TX
DMA_DMA2_SPI, // DMA2 Channel 4 - default channel for SPI
DMA_DMA2_UART_RX, // DMA2 Channel 5 - default channel for UART RX
DMA_DMA2_UART_TX, // DMA2 Channel 6 - default channel for UART TX
DMA_DMA2_7, // DMA2 Channel 7
DMA_DMA2_8, // DMA2 Channel 8
DMA_DMA2_9, // DMA2 Channel 9
DMA_DMA2_10, // DMA2 Channel 10
DMA_DMA2_11, // DMA2 Channel 11
DMA_MDMA2_D0, // DMA2 Memory DMA Stream 0 Destination.
DMA_MDMA2_S0, // DMA2 Memory DMA Stream 0 Source.
DMA_MDMA2_D1, // DMA2 Memory DMA Stream 1 Destination.
DMA_MDMA2_S1, // DMA2 Memory DMA Stream 1 Source.
DMA_IMDMA_D0, // IMDMA Stream 0 Destination.
DMA_IMDMA_S0, // IMDMA Stream 0 Source.
DMA_IMDMA_D1, // IMDMA Stream 1 Destination.
DMA_IMDMA_S1, // IMDMA Stream 1 Source.
DMA_CHANNEL_COUNT, // number of DMA channels
} DMA_TYPE_ID;
typedef enum { // Stream IDs for memory DMA
DMA_MDMA1_0, // memory DMA, controller 1, stream 0
DMA_MDMA1_1, // memory DMA, controller 1, stream 1
DMA_MDMA2_0, // memory DMA, controller 2, stream 0
DMA_MDMA2_1, // memory DMA, controller 2, stream 1
DMA_IMDMA_0, // internal memory DMA, stream 0
DMA_IMDMA_1, // internal memory DMA, stream 1
DMA_MEMORY_STREAM_COUNT, // number of memory DMA streams
} DMA_STREAM_ID;
#endif
typedef enum { // Buffer types
DEV_BUFFER_UNDEFINED, // undefined
DEV_1D, // 1 dimensional buffer
DEV_2D, // 2 dimensional buffer
DEV_CIRC, // circular buffer
DEV_SEQ_1D, // sequential 1 dimensional buffer
} DEV_BUFFER_TYPE;
class EJ_BBS
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