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📄 main.s

📁 AVR单片机系统开发经典实例部分源程序
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; 	UART1_RxBuffer[UART1_RxBufferWr++] = U1D;								// save new byte into the buffer
;     #endif
; 	#ifdef CPU_ATmega128
; 	UART1_RxBuffer[UART1_RxBufferWr++] = UDR1;								// save new byte into the buffer
	lds R2,_UART1_RxBufferWr
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _UART1_RxBufferWr,R24
	ldi R24,<_UART1_RxBuffer
	ldi R25,>_UART1_RxBuffer
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	lds R2,156
	std z+0,R2
	.dbline 384
;     #endif
; 	if (UART1_RxBufferWr >= sizeof(UART1_RxBuffer)) UART1_RxBufferWr = 0;	// wap awound
	lds R24,_UART1_RxBufferWr
	cpi R24,96
	brlo L115
	.dbline 384
	clr R2
	sts _UART1_RxBufferWr,R2
L115:
	.dbline 387
; 
; 	#ifdef ModemHandShaking
; 	HardwareFlowControl(UART1);												// tell em to hold it - if need be
	ldi R16,1
	xcall _HardwareFlowControl
	.dbline -2
L114:
	xcall pop_lset
	.dbline 0 ; func end
	reti
	.dbend
	.dbfunc e main _main fV
;              i -> R10,R11
;              j -> R12,R13
	.even
_main::
	sbiw R28,2
	.dbline -1
	.dbline 413
; 	#endif
; }
; 
; // *********************************************************************************
; /*
; #ifdef CPU_ATmega128
; void StackOverflowTest(u32 dw)
; {
; 	USB_Get();								// get data from USB
; 	USB_Send();								// send any data that needs sending via the USB
; 	USB_ProcessGet();						// process the rx'ed packet from the USB
; 
; 	_StackCheck();							// check for stack overflow
; 
; 	if (!WatchdogCounter) WatchdogCounter++;		//
; 
;    dw++;
; 	StackOverflowTest(dw);
; }
; #endif
; */
; // *********************************************************************************
; // Main program here
; 
; void main(void)
; {
	.dbline 416
; 	int		i, j;
; 
; 	Disable_Ints();
	cli
	.dbline 425
; 
; 	// ****************************
; 	// find out what caused the last reset
; 
; 	#ifdef CPU_eZ8
; 	LastResetReason = WDTCTL;
; 	#endif
; 	#ifdef CPU_ATmega128
; 	LastResetReason = MCUCSR;
	in R2,0x34
	sts _LastResetReason,R2
	.dbline 426
; 	MCUCSR &= 0xE0;					// clear the bits
	in R24,0x34
	andi R24,224
	out 0x34,R24
	.dbline 433
; 	#endif
; 
; 	// **********************
; 	// Define external memory mapping
; 
; 	#ifdef CPU_ATmega128
; 	asm(	".area memory(abs)\n"
	.area memory(abs)
	.org 0x1100
	 _SRAM:: .blkb 1
	.text
	
	.dbline 452
; 			".org 0x1100\n"
; 			" _SRAM:: .blkb 1\n"
; 			".text\n");
; 	#endif
; 
; 	// ****************************
; 	// set the watchdog timeout ASAP - you'll find the timeout value in common.h
; 	// see page 158 of the Z8F6423 product spec's pdf
; 	// the file config\Z8F6423.ini for the option bit settings - changing these makes no difference :(
; 
; 	#ifdef CPU_eZ8
; 	WDTCTL = 0x55;									// unlock the watchdog - so we can set it's time out
; 	WDTCTL = 0xAA;									//   "    "    "
; 	WDTU = (u8)((WatchdogTimeout >> 16) & 0xff);	// Set the timeout
; 	WDTH = (u8)((WatchdogTimeout >> 8) & 0xff);		//  "   "     "
; 	WDTL = (u8)(WatchdogTimeout & 0xff);			//  "   "     "
;     #endif
; 
; 	Reset_WD();
	wdr
	.dbline 455
; 
; 	#ifdef CPU_ATmega128
; 	WDTCR |= (1 << WDCE) | (1 << WDE);										// Enable watchdog config change
	in R24,0x21
	ori R24,24
	out 0x21,R24
	.dbline 456
; 	WDTCR = (1 << WDE) | (1 << WDP2) | (1 << WDP1) | (1 << WDP0);		// Enable watchdog to 2 second time out
	ldi R24,15
	out 0x21,R24
	.dbline 503
; 	#endif
; 
; 	// ****************************
; 	// disable all interrupts as default - or should i trust that the reset condition is reliable ?
; 
; 	#ifdef CPU_eZ8
; 	IRQ0ENH = 0;							// disable each individual interrupt
; 	IRQ0ENL = 0;							//
; 											//
; 	IRQ1ENH = 0;							//
; 	IRQ1ENL = 0;							//
; 											//
; 	IRQ2ENH = 0;							//
; 	IRQ2ENL = 0;							//
; 	#endif
; 
; 	// ****************************
; 	// set all ports to input state as default
; 
; 	#ifdef CPU_eZ8
; 	PADD = 0xff;	// as inputs
; 	PAADDR = 0;		// clear to protect sub registers
; 					//
; 	PBDD = 0xff;	// as inputs
; 	PBADDR = 0;		// clear to protect sub registers
; 					//
; 	PCDD = 0xff;	// as inputs
; 	PCADDR = 0;		// clear to protect sub registers
; 					//
; 	PDDD = 0xff;	// as inputs
; 	PDADDR = 0;		// clear to protect sub registers
; 					//
; 	PEDD = 0xff;	// as inputs
; 	PEADDR = 0;		// clear to protect sub registers
; 					//
; 	PFDD = 0xff;	// as inputs
; 	PFADDR = 0;		// clear to protect sub registers
; 					//
; 	PGDD = 0xff;	// as inputs
; 	PGADDR = 0;		// clear to protect sub registers
; 					//
; 	PHDD = 0xff;	// as inputs
; 	PHADDR = 0;		// clear to protect sub registers
; 	#endif
; 
; 	#ifdef CPU_ATmega128
;     PORTA = 0xff;	// enable pull-ups
	ldi R24,255
	out 0x1b,R24
	.dbline 504
;     DDRA = 0x00;	// as inputs
	clr R2
	out 0x1a,R2
	.dbline 506
; 
;     PORTB = 0xff;	// enable pull-ups
	out 0x18,R24
	.dbline 507
;     DDRB = 0x00;	// as inputs
	out 0x17,R2
	.dbline 509
; 
;     PORTC = 0xff;	// enable pull-ups
	out 0x15,R24
	.dbline 510
;     DDRC = 0x00;	// as inputs
	out 0x14,R2
	.dbline 512
; 
;     PORTD = 0xff;	// enable pull-ups
	out 0x12,R24
	.dbline 513
;     DDRD = 0x00;	// as inputs
	out 0x11,R2
	.dbline 515
; 
;     PORTE = 0xff;	// enable pull-ups
	out 0x3,R24
	.dbline 516
;     DDRE = 0x00;	// as inputs
	out 0x2,R2
	.dbline 518
; 
;     PORTF = 0xfc;	// enable pull-ups
	ldi R24,252
	sts 98,R24
	.dbline 519
;     DDRF = 0x00;	// as inputs
	sts 97,R2
	.dbline 521
; 
;     PORTG = 0xff;	// enable pull-ups
	ldi R24,255
	sts 101,R24
	.dbline 522
;     DDRG = 0x00;	// as inputs
	sts 100,R2
	.dbline 528
; 	#endif
; 
; 	// ****************************
; 	// delay a bit - stops irratic boot-ups when programming etc
; 
; 	for (i = 0; i < 25; i++)
	clr R10
	clr R11
L118:
	.dbline 529
; 	{
	.dbline 530
; 		for (j = 0; j < 32767; j++)
	clr R12
	clr R13
L122:
	.dbline 531
	.dbline 532
	wdr
	.dbline 533
L123:
	.dbline 530
	movw R24,R12
	adiw R24,1
	movw R12,R24
	.dbline 530
	cpi R24,255
	ldi R30,127
	cpc R25,R30
	brlt L122
	.dbline 534
L119:
	.dbline 528
	movw R24,R10
	adiw R24,1
	movw R10,R24
	.dbline 528
	cpi R24,25
	ldi R30,0
	cpc R25,R30
	brlt L118
	.dbline 566
; 		{
; 			Reset_WD();
; 		}
; 	}
; 
; 	// ****************************
; 
; 	#ifdef CPU_eZ8
; 	RLed_ddPort &= ~(1 << RLed_Pin);		// set as output
; 	RLed_hdePort &= ~(1 << RLed_Pin);		// disable high drive
; 	RLed_addrPort = 0;						// clear to protect sub registers
; 	RLed_Off;								//
; 
; 	YLed_ddPort &= ~(1 << YLed_Pin);		// set as output
; 	YLed_hdePort &= ~(1 << YLed_Pin);		// disable high drive
; 	YLed_addrPort = 0;						// clear to protect sub registers
; 	YLed_Off;								//
; 
; 	GLed_ddPort &= ~(1 << GLed_Pin);		// set as output
; 	GLed_hdePort &= ~(1 << GLed_Pin);		// disable high drive
; 	GLed_addrPort = 0;						// clear to protect sub registers
; 	GLed_Off;								//
; 
; 	RTS0_ddPort &= ~(1 << RTS0_Pin);		// set as output
; 	RTS0_hdePort &= ~(1 << RTS0_Pin);		// disable high drive
; 	RTS0_addrPort = 0;						// clear to protect sub registers
; 	RTS0_OK;								//
; 
; 	RTS1_ddPort &= ~(1 << RTS1_Pin);		// set as output
; 	RTS1_hdePort &= ~(1 << RTS1_Pin);		// disable high drive
; 	RTS1_addrPort = 0;						// clear to protect sub registers
; 	RTS1_OK;								//
;     #endif
; 
; 	#ifdef CPU_ATmega128
; 	sbi(RLed_ddPort,  RLed_Pin);			// set as output
	sbi 0x17,5
	.dbline 567
; 	RLed_Off;								//
	sbi 0x18,5
	.dbline 569
; 
; 	sbi(YLed_ddPort, YLed_Pin);				// set as output
	sbi 0x17,6
	.dbline 570
; 	YLed_Off;								//
	sbi 0x18,6
	.dbline 572
; 
; 	sbi(GLed_ddPort, GLed_Pin);				// set as output
	sbi 0x17,7
	.dbline 573
; 	GLed_Off;								//
	sbi 0x18,7
	.dbline 575
; 
; 	sbi(SS_ddPort, SS_Pin);					// set as output
	sbi 0x17,0
	.dbline 576
; 	sbi(SS_oPort, SS_Pin);					// set high
	sbi 0x18,0
	.dbline 578
; 
; 	sbi(SCLK_ddPort, SCLK_Pin);				// set as output
	sbi 0x17,1
	.dbline 579
; 	sbi(SCLK_oPort, SCLK_Pin);				// set high
	sbi 0x18,1
	.dbline 581
; 
; 	sbi(MOSI_ddPort, MOSI_Pin);				// set as output
	sbi 0x17,2
	.dbline 582
; 	sbi(MOSI_oPort, MOSI_Pin);				// set high
	sbi 0x18,2
	.dbline 584
; 
; 	sbi(TXD0_ddPort, TXD0_Pin);				// set as output
	sbi 0x2,1
	.dbline 585
; 	sbi(TXD0_oPort, TXD0_Pin);				// set high
	sbi 0x3,1
	.dbline 587
; 
; 	sbi(RTS0_ddPort, RTS0_Pin);				// set as output
	sbi 0x2,3
	.dbline 588
; 	RTS0_OK;								//
	cbi 0x3,3
	.dbline 590
; 
; 	sbi(TXD1_ddPort, TXD1_Pin);				// set as output
	sbi 0x11,3
	.dbline 591
; 	sbi(TXD1_oPort, TXD1_Pin);				// set high
	sbi 0x12,3
	.dbline 593
; 
; 	sbi(RTS1_ddPort, RTS1_Pin);				// set as output
	sbi 0x11,5
	.dbline 594
; 	RTS1_OK;								//
	cbi 0x12,5
	.dbline 596
; 
; 	sbi(SRAM_CS_ddPort, SRAM_CS_Pin);		// set as output
	sbi 0x14,7
	.dbline 597
; 	SRAM_Disable;							//
	sbi 0x15,7
	.dbline 603
; 	#endif
; 
; 	// ****************************
; 
; 	#ifdef CPU_ATmega128
; 	XDIV = 0;											// xtal divider - run at xtal clock freq
	clr R2
	out 0x3c,R2
	.dbline 605
; 	   													//
; 	EICRA = 0;											// no extended ext ints
	sts 106,R2
	.dbline 606
; 	EICRB = 0;											// no extended ext ints
	out 0x3a,R2
	.dbline 607
; 	EIMSK = 0;											// no external ints (INT0-INT7)
	out 0x39,R2
	.dbline 608
; 	EIFR = 0;											//
	out 0x38,R2
	.dbline 610
;    														//
; 	MCUCR = (1<<SRE);									// enable external memory
	ldi R24,128
	out 0x35,R24
	.dbline 611
; 	XMCRA = (1<<SRL2)|(1<<SRL0);						// lower sector = 0x1100 - 0x9fff .. no wait states
	ldi R24,80
	sts 109,R24
	.dbline 615
; //   XMCRA = (1<<SRL2)|(1<<SRL0)|(1<<SW00);				// lower sector = 0x1100 - 0x9fff .. 1 wait state
; //   XMCRA = (1<<SRL2)|(1<<SRL0)|(1<<SW01);				// lower sector = 0x1100 - 0x9fff .. 2 wait states
; //   XMCRA = (1<<SRL2)|(1<<SRL0)|(1<<SW01)|(1<<SW00);	// lower sector = 0x1100 - 0x9fff .. 2 wait states during read/write, wait one cycle before driving out new address
; 	XMCRB = (1<<XMM0);									// leave pin PC7 free for user use
	ldi R24,1
	sts 108,R24
	.dbline 617
; 														//
; 	ASSR = 0;											//
	out 0x30,R2
	.dbline 619
; 														//
; 	TIMSK = 0;											// timer interrupt sources
	out 0x37,R2
	.dbline 620
; 	ETIMSK = 0;											// extended timer interrupt sources
	sts 125,R2
	.dbline 640
; 	#endif
; 
; 	// ****************************
; 	// setup a 10ms timer interrupt
; 
; 	#ifdef CPU_eZ8
; 	// Initialize Timer-0
; 	SET_VECTOR(TIMER0, isr_timer0); 		// Set timer interrupt vector
;  	T0H		= (u8)(TimerIntSpeed >> 8);		// Timer High
; 	T0L 	= (u8)(TimerIntSpeed & 0xff);	// Timer Low
; 	T0RH 	= (u8)(TimerIntSpeed >> 8);		// Reload Compare High
; 	T0RL 	= (u8)(TimerIntSpeed & 0xff);	// Reload Compare Low
; 	T0CTL 	= (1<<TEN)|(1<<TPOL)|(1<<PRES2)|(1<<PRES1)|(1<<PRES0)|(1<<TMODE0);			// Enabled, clk/128, Continous mode
; 	IRQ0ENH |= (1<<T0EN);					// Set Interrupt Priority Nominal
; 	IRQ0ENL &= ~(1<<T0EN);					//  "
;     #endif
; 
; 	#ifdef CPU_ATmega128
; 	// Initialize Timer-1
; 	TCCR1B = 0;								// stop
	out 0x2e,R2
	.dbline 642
;    											//
; 	TCNT1 = TimerIntSpeed;					// reload counter high value
	ldi R24,56320
	ldi R25,220
	out 0x2d,R25
	out 0x2c,R24
	.dbline 646
; //	TCNT1H = (u8)(TimerIntSpeed >> 8);		// reload counter high value
; //	TCNT1L = (u8)(TimerIntSpeed & 0xff);	//   "
;    											//
; 	OCR1A = 9216;							//
	ldi R25,36
	out 0x2b,R25
	out 0x2a,R24
	.dbline 647
; 	OCR1B = 9216;							//
	out 0x29,R25
	out 0x28,R24
	.dbline 648
; 	OCR1C = 9216;							//
	sts 120+1,R25
	sts 120,R24
	.dbline 649
; 	ICR1 = 9216;							//
	out 0x27,R25
	out 0x26,R24
	.dbline 651
;    											//
; 	TCCR1A = 0;								//
	out 0x2f,R2
	.dbline 652
; 	TCCR1B = (1<<CS11);						// start Timer, MainClk/8
	ldi R24,2
	out 0x2e,R24
	.dbline 654
; 											//
; 	sbi(TIMSK, TOIE1);						// Enable timer overflow interupt
	in R24,0x37
	ori R24,4
	out 0x37,R24
	.dbline 660
; 	#endif
; 
; 	// ****************************
; 	// Initialize Uart-0 (Console/Debug terminal)
; 
; 	InitUart(UART0, UART0_BaudRate);		// Setup uart
	ldi R20,0
	ldi R21,194
	ldi R22,1
	ldi R23,0
	std y+0,R22
	std y+1,R23
	movw R18,R20
	clr R16
	xcall _InitUart
	.dbline 672
; 
; 	#ifdef CPU_eZ8
; 	SET_VECTOR(UART0_RX, isr_uart0_rx);		// setup an RX interrupt
; 											//
; 	IRQ0ENH |= (1<<U0REN);					// Set Interrupt Priority normal
; 	IRQ0ENL &= ~(1<<U0REN);					//  "
;     #endif
; 
; 	// ****************************
; 	// Initialize Uart-1 (PPP)
; 
; 	InitUart(UART1, UART1_BaudRate);		// Setup uart
	ldi R20,0
	ldi R21,75
	ldi R22,0
	ldi R23,0
	std y+0,R22
	std y+1,R23
	movw R18,R20
	ldi R16,1
	xcall _InitUart
	.dbline 684
;
1234

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