📄 main.s
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; { //
.dbline 209
; sbi(ADCSRA, ADSC); // Start the next conversion
sbi 0x6,6
.dbline 210
; Flags1 &= ~(1<<Flags1_ADC); // clear flag
lds R24,_Flags1
andi R24,191
sts _Flags1,R24
.dbline 211
; } //
xjmp L62
L61:
.dbline 213
; else //
; { //
.dbline 214
; w = (u16)ADCL; // read LS-Byte
in R22,0x4
clr R23
.dbline 215
; w |= ((u16)ADCH) << 8; // read MS-Byte
in R2,0x5
clr R3
mov R3,R2
clr R2
or R22,R2
or R23,R3
.dbline 217
; //
; i = (u16)(ADMUX & 0x07); // current ADC channel
in R20,0x7
clr R21
andi R20,7
andi R21,0
.dbline 219
; //
; w += ADC_Input[i]; //
ldi R16,2
ldi R17,0
movw R18,R20
xcall empy16s
movw R30,R16
ldi R24,<_ADC_Input
ldi R25,>_ADC_Input
add R30,R24
adc R31,R25
ldd R2,z+0
ldd R3,z+1
add R22,R2
adc R23,R3
.dbline 220
; w >>= 1; // average with previous value - helps with noise
lsr R23
ror R22
.dbline 221
; ADC_Input[i] = w; // save the new value
ldi R16,2
ldi R17,0
movw R18,R20
xcall empy16s
movw R30,R16
ldi R24,<_ADC_Input
ldi R25,>_ADC_Input
add R30,R24
adc R31,R25
std z+1,R23
std z+0,R22
.dbline 223
; //
; i++; // next ADC channel
subi R20,255 ; offset = 1
sbci R21,255
.dbline 224
; if (i > 1) i = 0; // only interested in channels 0 and 1
ldi R24,1
ldi R25,0
cp R24,R20
cpc R25,R21
brsh L63
.dbline 224
clr R20
clr R21
L63:
.dbline 226
; // if (i > 7) i = 0; // only interested in channels 0 to 7
; ADMUX = (u8)i; // select it
out 0x7,R20
.dbline 228
; //
; Flags1 |= (1<<Flags1_ADC); // set flag - this tells the next timer int to start the new conversion.
lds R24,_Flags1
ori R24,64
sts _Flags1,R24
.dbline 231
; // we leave starting the next conversion to the next timer int so as to
; // allow the ADC input to settle to the newly selected input pin
; }
L62:
.dbline 232
; }
L59:
.dbline 237
; #endif
;
; // *************************
;
; AT_10ms_Timer();
xcall _AT_10ms_Timer
.dbline 238
; PPP_10ms_Timer();
xcall _PPP_10ms_Timer
.dbline 243
;
; // *************************
; // Test button debounce
;
; if (!TestButton) button_push = 0; // button is pressed - reset the debounce detector
sbic 0x10,0
rjmp L65
.dbline 243
clr R2
sts _button_push,R2
xjmp L66
L65:
.dbline 245
; else
; {
.dbline 246
; if (button_push < 255) button_push++; // update the debounce counter
lds R24,_button_push
cpi R24,255
brsh L67
.dbline 246
lds R24,_button_push
subi R24,255 ; addi 1
sts _button_push,R24
L67:
.dbline 247
; if (button_push == button_debounce) Flags1 |= (1<<Flags1_ButtonPress); // button has just been released
lds R24,_button_push
cpi R24,8
brne L69
.dbline 247
lds R24,_Flags1
ori R24,4
sts _Flags1,R24
L69:
.dbline 248
; }
L66:
.dbline 253
;
; //**********************************
; // do stuff with the led's
;
; switch (AT.Stage)
lds R20,_AT+3
clr R21
cpi R20,0
cpc R20,R21
breq L75
X2:
cpi R20,0
ldi R30,0
cpc R21,R30
brlt L71
L83:
cpi R20,5
ldi R30,0
cpc R21,R30
breq L78
xjmp L71
X3:
.dbline 254
; {
L75:
.dbline 255
; case AT_Idle : if (TimerIntCounter & 0x20)
lds R2,_TimerIntCounter
sbrs R2,5
rjmp L76
.dbline 256
; RLed_On;
cbi 0x18,5
xjmp L72
L76:
.dbline 258
; else
; RLed_Off;
sbi 0x18,5
.dbline 259
; break;
xjmp L72
L78:
.dbline 260
; case AT_PPP : if (TimerIntCounter & 0x50)
lds R24,_TimerIntCounter
andi R24,80
breq L79
.dbline 261
; RLed_On;
cbi 0x18,5
xjmp L72
L79:
.dbline 263
; else
; RLed_Off;
sbi 0x18,5
.dbline 264
; break;
xjmp L72
L71:
.dbline 265
; default : if (TimerIntCounter & 0x10)
lds R2,_TimerIntCounter
sbrs R2,4
rjmp L81
.dbline 266
; RLed_On;
cbi 0x18,5
xjmp L72
L81:
.dbline 268
; else
; RLed_Off;
sbi 0x18,5
.dbline 269
; break;
L72:
.dbline 272
; }
;
; switch (PPP.Stage)
lds R20,_PPP+9
clr R21
cpi R20,0
cpc R20,R21
breq L88
X4:
cpi R20,0
ldi R30,0
cpc R21,R30
brlt L84
L94:
cpi R20,5
ldi R30,0
cpc R21,R30
breq L89
xjmp L84
X5:
.dbline 273
; {
L88:
.dbline 274
; case PPPS_None : YLed_Off;
sbi 0x18,6
.dbline 275
; break;
xjmp L85
L89:
.dbline 276
; case PPPS_IP : if (TimerIntCounter & 0x50)
lds R24,_TimerIntCounter
andi R24,80
breq L90
.dbline 277
; YLed_On;
cbi 0x18,6
xjmp L85
L90:
.dbline 279
; else
; YLed_Off;
sbi 0x18,6
.dbline 280
; break;
xjmp L85
L84:
.dbline 281
; default : if (TimerIntCounter & 0x04)
lds R2,_TimerIntCounter
sbrs R2,2
rjmp L92
.dbline 282
; YLed_On;
cbi 0x18,6
xjmp L85
L92:
.dbline 284
; else
; YLed_Off;
sbi 0x18,6
.dbline 285
; break;
L85:
.dbline 302
; }
;
; // CTS0 state
; // if (CTS0) //
; // GLed_Off; //
; // else //
; // GLed_On; //
;
; // CTS1 state
; // if (CTS1) //
; // GLed_Off; //
; // else //
; // GLed_On; //
;
; // TCP socket state
; #ifdef IncludeTCP
; if (TCP_Socket != NULL) //
lds R2,_TCP_Socket
lds R3,_TCP_Socket+1
tst R2
brne X6
tst R3
breq L95
X6:
.dbline 303
; { //
.dbline 304
; switch (TCP_Socket->Stage) //
lds R30,_TCP_Socket
lds R31,_TCP_Socket+1
ldd R20,z+0
clr R21
cpi R20,0
cpc R20,R21
breq L100
X7:
cpi R20,1
ldi R30,0
cpc R21,R30
breq L101
cpi R20,4
ldi R30,0
cpc R21,R30
breq L104
xjmp L97
X8:
.dbline 305
; { //
L100:
.dbline 306
; case TCP_CLOSED : GLed_Off; //
sbi 0x18,7
.dbline 307
; break; //
xjmp L96
L101:
.dbline 308
; case TCP_LISTEN : if (TimerIntCounter & 0x20) //
lds R2,_TimerIntCounter
sbrs R2,5
rjmp L102
.dbline 309
; GLed_On; //
cbi 0x18,7
xjmp L96
L102:
.dbline 311
; else //
; GLed_Off; //
sbi 0x18,7
.dbline 312
; break; //
xjmp L96
L104:
.dbline 313
; case TCP_ESTABLISHED : if (TimerIntCounter & 0x50) //
lds R24,_TimerIntCounter
andi R24,80
breq L105
.dbline 314
; GLed_On; //
cbi 0x18,7
xjmp L96
L105:
.dbline 316
; else //
; GLed_Off; //
sbi 0x18,7
.dbline 317
; break; //
xjmp L96
L97:
.dbline 318
; default : if (TimerIntCounter & 0x10) //
lds R2,_TimerIntCounter
sbrs R2,4
rjmp L107
.dbline 319
; GLed_On; //
cbi 0x18,7
xjmp L96
L107:
.dbline 321
; else //
; GLed_Off; //
sbi 0x18,7
.dbline 322
; break; //
.dbline 324
; } //
; } //
xjmp L96
L95:
.dbline 326
; else //
; GLed_Off; //
sbi 0x18,7
L96:
.dbline 336
lds R24,_WatchdogCounter
cpi R24,1
brne L109
.dbline 337
.dbline 338
wdr
.dbline 339
clr R2
sts _WatchdogCounter,R2
.dbline 340
L109:
.dbline -2
L58:
adiw R28,1
xcall pop_gset2
xcall pop_lset
.dbline 0 ; func end
reti
.dbsym r w 22 s
.dbsym r i 20 s
.dbend
.area vector(rom, abs)
.org 72
jmp _isr_uart0_rx
.area text(rom, con, rel)
.dbfile C:\AVR\AT-Modem__PPP__UDP__IC\main.c
.dbfunc e isr_uart0_rx _isr_uart0_rx fV
.even
_isr_uart0_rx::
xcall push_lset
.dbline -1
.dbline 353
; #else
; GLed_Off; //
; #endif
;
; // *************************
; // keep the watchdog at bay.
; // the WatchdogCounter variable is set in the executive - this makes resetting the WD a co-op affair between the exec and this interrupt.
; // keep this code as the last thing to be done in the interrupt - incase a loop/dead-lock occurs before we get this far
;
; if (WatchdogCounter == 1) //
; { //
; Reset_WD(); // Keep the watchdog at bay
; WatchdogCounter = 0; //
; }
; }
;
; // *********************************************************************************
; // Uart-0 Rx Interrupt routine
;
; #ifdef CPU_eZ8
; #pragma interrupt
; #endif
; #ifdef CPU_ATmega128
; #pragma interrupt_handler isr_uart0_rx:19
; #endif
; void isr_uart0_rx(void)
; {
.dbline 358
; #ifdef CPU_eZ8
; UART0_RxBuffer[UART0_RxBufferWr++] = U0D; // save new byte into the buffer
; #endif
; #ifdef CPU_ATmega128
; UART0_RxBuffer[UART0_RxBufferWr++] = UDR0; // save new byte into the buffer
lds R2,_UART0_RxBufferWr
clr R3
mov R24,R2
subi R24,255 ; addi 1
sts _UART0_RxBufferWr,R24
ldi R24,<_UART0_RxBuffer
ldi R25,>_UART0_RxBuffer
mov R30,R2
clr R31
add R30,R24
adc R31,R25
in R2,0xc
std z+0,R2
.dbline 360
; #endif
; if (UART0_RxBufferWr >= sizeof(UART0_RxBuffer)) UART0_RxBufferWr = 0; // wap awound
lds R24,_UART0_RxBufferWr
cpi R24,32
brlo L112
.dbline 360
clr R2
sts _UART0_RxBufferWr,R2
L112:
.dbline 363
;
; #ifdef ConsoleHandShaking
; HardwareFlowControl(UART0); // tell em to hold it - if need be
clr R16
xcall _HardwareFlowControl
.dbline -2
L111:
xcall pop_lset
.dbline 0 ; func end
reti
.dbend
.area vector(rom, abs)
.org 120
jmp _isr_uart1_rx
.area text(rom, con, rel)
.dbfile C:\AVR\AT-Modem__PPP__UDP__IC\main.c
.dbfunc e isr_uart1_rx _isr_uart1_rx fV
.even
_isr_uart1_rx::
xcall push_lset
.dbline -1
.dbline 377
; #endif
; }
;
; // *********************************************************************************
; // Uart-1 Rx Interrupt routine
;
; #ifdef CPU_eZ8
; #pragma interrupt
; #endif
; #ifdef CPU_ATmega128
; #pragma interrupt_handler isr_uart1_rx:31
; #endif
; void isr_uart1_rx(void)
; {
.dbline 382
; #ifdef CPU_eZ8
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