📄 common.s
字号:
sbci R17,255
L112:
.dbline 581
; for (; *s; s++) len++;
movw R30,R16
lpm R30,Z
tst R30
brne L109
.dbline 582
; }
L107:
.dbline 583
; return len;
movw R16,R20
.dbline -2
L106:
xcall pop_gset1
.dbline 0 ; func end
ret
.dbsym r len 20 I
.dbsym r s 16 pkc
.dbend
.dbfunc e rstrcpy _rstrcpy fV
; src -> R18,R19
; dest -> R16,R17
.even
_rstrcpy::
.dbline -1
.dbline 587
; }
;
; void rstrcpy(char *dest, RomChar *src)
; { // copy a flash (rom) string into data memory
.dbline 588
; if (!dest) return; // tut tut
cpi R16,0
cpc R16,R17
brne L114
X12:
.dbline 588
xjmp L113
L114:
.dbline 589
; if (src)
cpi R18,0
cpc R18,R19
breq L116
X13:
.dbline 590
; {
.dbline 591
xjmp L121
L118:
.dbline 591
movw R2,R18
subi R18,255 ; offset = 1
sbci R19,255
movw R30,R2
lpm R30,Z
movw R26,R16
st X+,R30
movw R16,R26
L119:
.dbline 591
L121:
.dbline 591
; for (; *src; ) *dest++ = *src++;
movw R30,R18
lpm R30,Z
tst R30
brne L118
.dbline 592
; }
L116:
.dbline 593
; *dest = 0; // null terminate it
clr R2
movw R30,R16
std z+0,R2
.dbline -2
L113:
.dbline 0 ; func end
ret
.dbsym r src 18 pkc
.dbsym r dest 16 pc
.dbend
.dbfunc e rmemcpy _rmemcpy fV
; len -> R20,R21
; src -> R18,R19
; dest -> R16,R17
.even
_rmemcpy::
xcall push_gset1
ldd R20,y+2
ldd R21,y+3
.dbline -1
.dbline 597
; }
;
; void rmemcpy(char *dest, RomChar *src, int len)
; { // copy a block of data from flash (rom) into data memory
.dbline 598
; if (!dest) return;
cpi R16,0
cpc R16,R17
brne L123
X14:
.dbline 598
xjmp L122
L123:
.dbline 599
; if (!src) return;
cpi R18,0
cpc R18,R19
brne L130
X15:
.dbline 599
xjmp L122
X16:
.dbline 600
L127:
.dbline 600
movw R2,R18
subi R18,255 ; offset = 1
sbci R19,255
movw R30,R2
lpm R30,Z
movw R26,R16
st X+,R30
movw R16,R26
L128:
.dbline 600
subi R20,1
sbci R21,0
L130:
.dbline 600
; for (; len; len--) *dest++ = *src++;
cpi R20,0
cpc R20,R21
brne L127
X17:
.dbline -2
L122:
xcall pop_gset1
.dbline 0 ; func end
ret
.dbsym r len 20 I
.dbsym r src 18 pkc
.dbsym r dest 16 pc
.dbend
.dbfunc e SPI_Init _SPI_Init fV
.even
_SPI_Init::
.dbline -1
.dbline 607
; }
;
; // *********************************************************************************
; // SPI stuff
;
; void SPI_Init(void)
; { // setup the spi
.dbline 625
;
; #ifdef CPU_eZ8
; // PCAF = 0x3c; // Enable Port C for SPI functions
; // PCADDR = 0; // protect sub registers
;
; // SPICTL = PHASE_ONE | MMEN_MASTER | SPI_ENABLE; // SCK Phase One, SPI Master, SPI enable,
; // CLK Polarity=0->falling edge for internal strobe
; // SPIMODE = SSIO_OUTPUT; // SS pin select as an output, SS pin low
; // SPIBRH = 0x00; // BRG High
; // SPIBRL = 0x9c; // BRG Low
; asm("nop");
; #endif
;
; #ifdef CPU_ATmega128
; // SPI initialisation
; // clock rate: 3686400hz (with 7.3728Mhz xtal)
;
; SPCR = 0; // disable SPI
clr R2
out 0xd,R2
.dbline 626
; SPSR = (1 << SPI2X); // 2X
ldi R24,1
out 0xe,R24
.dbline 627
; SPCR = (1 << SPE) | (1 << MSTR); // enable SPI ... no interrupt, SPI enable, MSB 1st, Master mode, Fosc/2
ldi R24,80
out 0xd,R24
.dbline -2
L131:
.dbline 0 ; func end
ret
.dbend
.dbfunc e SPI_TxRxByte _SPI_TxRxByte fc
; i -> R20
; o -> R16
.even
_SPI_TxRxByte::
xcall push_gset1
.dbline -1
.dbline 641
;
; // SPDR = 0x55; // sends a 0x55 byte out the spi
; // while (bit_is_clr(SPSR, SPIF)); // wait for transmission to finish
; // c = SPDR; // this is needed
;
; // SPDR = 0; // write a dummy byte - this is to generate the SCK for reading
; // while (bit_is_clr(SPSR, SPIF)); // wait for rx byte to arrive
; // c = SPDR; // reads a rx'ed byte
; #endif
;
; }
;
; u8 SPI_TxRxByte(u8 o)
; { // send and receive bytes to/from the spi
.dbline 649
; u8 i; //
;
; #ifdef CPU_eZ8
; i = 0;
; #endif
;
; #ifdef CPU_ATmega128
; SPDR = o; // send byte down spi
out 0xf,R16
L133:
.dbline 650
L134:
.dbline 650
; while (!(SPSR & (1<<SPIF))); // wait for byte to go
sbis 0xe,7
rjmp L133
.dbline 651
; i = SPDR; // get byte from spi
in R20,0xf
.dbline 654
; #endif
;
; return i; // return byte got
mov R16,R20
.dbline -2
L132:
xcall pop_gset1
.dbline 0 ; func end
ret
.dbsym r i 20 c
.dbsym r o 16 c
.dbend
.dbfunc e InitUart _InitUart fV
; brg -> R10,R11
; baud -> y+8
; port -> R12
.even
_InitUart::
st -y,r19
st -y,r18
xcall push_gset4
mov R12,R16
.dbline -1
.dbline 706
; }
;
; // *********************************************************************************
; // uart stuff
;
; #ifdef CPU_eZ8
; void InitUart(char port, unsigned long baud)
; {
; unsigned long brg;
;
; // calculate the divider value
; brg = MainClk / (baud * 16);
;
; switch (port)
; {
; case UART0 : // set the baud-rate generater
; U0BRH = brg >> 8;
; U0BRL = brg & 0xFF;
;
; // configure GPIO for alternate function
; PAAF |= 0x30; // enable the UART0 Rx/Tx with the AF register
; PAADDR = 0; // clear to protect sub-regiters
;
; // configure UART control register 1
; U0CTL1 = 0x00; // clear for normal non-Multiprocessor operation
;
; // configure UART control register 1
; U0CTL0 = 0xc0; // Transmit enable, Receive Enable, No Parity, 1 Stop
; break;
; case UART1 : // set the baud-rate generater
; U1BRH = brg >> 8;
; U1BRL = brg & 0xFF;
;
; // configure GPIO for alternate function
; PDAF |= 0x30; // enable the UART1 Rx/Tx with the AF register
; PDADDR = 0; // clear to protect sub-regiters
;
; // configure UART control register 1
; U1CTL1 = 0x00; // clear for normal non-Multiprocessor operation
;
; // configure UART control register 1
; U1CTL0 = 0xc0; // Transmit enable, Receive Enable, No Parity, 1 Stop
; break;
; }
; }
;
; #endif
;
; #ifdef CPU_ATmega128
;
; void InitUart(char port, unsigned long baud)
; {
.dbline 710
; u16 brg;
;
; // calculate the divider value
; brg = (MainClk / (baud * 8)) - 1; // double speed formula
movw R30,R28
ldd R2,z+8
ldd R3,z+9
ldd R4,z+10
ldd R5,z+11
ldi R20,8
ldi R21,0
ldi R22,0
ldi R23,0
st -y,R5
st -y,R4
st -y,R3
st -y,R2
movw R16,R20
movw R18,R22
xcall empy32u
ldi R20,0
ldi R21,128
ldi R22,112
ldi R23,0
st -y,R19
st -y,R18
st -y,R17
st -y,R16
movw R16,R20
movw R18,R22
xcall div32u
movw R2,R16
movw R4,R18
ldi R20,1
ldi R21,0
ldi R22,0
ldi R23,0
sub R2,R20
sbc R3,R21
sbc R4,R22
sbc R5,R23
movw R10,R2
.dbline 712
;
; switch (port)
clr R13
tst R12
brne X18
tst R13
breq L140
X18:
movw R24,R12
cpi R24,1
ldi R30,0
cpc R25,R30
breq L141
xjmp L137
X19:
.dbline 713
; {
L140:
.dbline 715
; case UART0 : // 8-bit 1-stop no-parity async ... 7 = 115200 baud
; UCSR0B = 0; // disable while setting it up
clr R2
out 0xa,R2
.dbline 717
;
; UBRR0H = (u8)(brg >> 8); // set baud rate hi
movw R2,R10
mov R2,R3
clr R3
sts 144,R2
.dbline 718
; UBRR0L = (u8)(brg & 0xff); // set baud rate lo
movw R24,R10
andi R25,0
out 0x9,R24
.dbline 720
;
; UCSR0A = (1<<U2X0); // double speed
ldi R24,2
out 0xb,R24
.dbline 721
; UCSR0C = (1<<UCSZ00)|(1<<UCSZ01)|(1<<UCSZ00); // 8-bit 1-stop
ldi R24,6
sts 149,R24
.dbline 722
; UCSR0B = (1<<RXCIE0)|(1<<RXEN0)|(1<<TXEN0); // enable Tx/Rx
ldi R24,152
out 0xa,R24
.dbline 724
;
; break;
xjmp L138
L141:
.dbline 726
; case UART1 : // 8-bit 1-stop no-parity async .. 47 = 19200 baud
; UCSR1B = 0; // disable while setting baud rate
clr R2
sts 154,R2
.dbline 728
;
; UBRR1H = (u8)(brg >> 8); //set baud rate hi
movw R2,R10
mov R2,R3
clr R3
sts 152,R2
.dbline 729
; UBRR1L = (u8)(brg & 0xff); //set baud rate lo
movw R24,R10
andi R25,0
sts 153,R24
.dbline 731
;
; UCSR1A = (1<<U2X1); // double speed
ldi R24,2
sts 155,R24
.dbline 732
; UCSR1C = (1<<UCSZ10)|(1<<UCSZ11)|(1<<UCSZ10); // 8-bit 1-stop
ldi R24,6
sts 157,R24
.dbline 733
; UCSR1B = (1<<RXCIE1)|(1<<RXEN1)|(1<<TXEN1); // enable Tx/Rx
ldi R24,152
sts 154,R24
.dbline 734
; break;
L137:
L138:
.dbline -2
L136:
xcall pop_gset4
adiw R28,2
.dbline 0 ; func end
ret
.dbsym r brg 10 s
.dbsym l baud 8 l
.dbsym r port 12 c
.dbend
.dbfunc e SendUartByte _SendUartByte fc
; UART_TimeOut -> R20,R21
; Uart -> R18
; c -> R16
.even
_SendUartByte::
xcall push_gset2
.dbline -1
.dbline 741
; }
; }
;
; #endif
;
; bool SendUartByte(char c, char Uart)
; { // send a byte down a uart
.dbline 742
; u16 UART_TimeOut = 10000;
ldi R20,10000
ldi R21,39
.dbline 744
;
; switch (Uart)
mov R22,R18
clr R23
cpi R22,0
cpc R22,R23
breq L148
X20:
cpi R22,1
ldi R30,0
cpc R23,R30
breq L158
xjmp L143
X21:
.dbline 745
; {
L147:
.dbline 747
; case UART0 : while (true)
; {
.dbline 748
; UART_TimeOut--;
subi R20,1
sbci R21,0
.dbline 749
; if (!UART_TimeOut) return false; // timed out
brne L150
X22:
.dbline 749
clr R16
xjmp L142
L150:
.dbline 752
;
; #ifdef ConsoleHandShaking
; if (CTS0) continue; // other end not yet ready
sbis 0x1,2
rjmp L152
.dbline 752
xjmp L148
L152:
.dbline 760
; #endif
;
; #ifdef CPU_eZ8
; if (U0STAT0 & 0x04) break; // clear to send another byte
; #endif
;
; #ifdef CPU_ATmega128
; if (UCSR0A & (1 << UDRE0)) break; // clear to send another byte
sbis 0xb,5
rjmp L154
.dbline 760
xjmp L149
L154:
.dbline 762
L148:
.dbline 746
xjmp L147
L149:
.dbline 767
; #endif
; }
; #ifdef CPU_eZ8
; U0D = c; // Send byte
; #endif
; #ifdef CPU_ATmega128
; UDR0 = c; // Send byte
out 0xc,R16
.dbline 769
; #endif
; break;
xjmp L144
L157:
.dbline 771
; case UART1 : while (true)
; {
.dbline 772
; UART_TimeOut--;
subi R20,1
sbci R21,0
.dbline 773
; if (!UART_TimeOut) return false; // timed out
brne L160
X23:
.dbline 773
clr R16
xjmp L142
L160:
.dbline 776
;
; #ifdef ModemHandShaking
; if (CTS1) continue; // other end not yet ready
sbis 0x10,4
rjmp L162
.dbline 776
xjmp L158
L162:
.dbline 784
; #endif
;
; #ifdef CPU_eZ8
; if (U1STAT0 & 0x04) break; // clear to send another byte
; #endif
;
; #ifdef CPU_ATmega128
; if (UCSR1A & (1 << UDRE1)) break; // clear to send another byte
lds R2,155
sbrs R2,5
rjmp L164
.dbline 784
xjmp L159
L164:
.dbline 786
L158:
.dbline 770
xjmp L157
L159:
.dbline 791
; #endif
; }
; #ifdef CPU_eZ8
; U1D = c; // Send byte
; #endif
; #ifdef CPU_ATmega128
; UDR1 = c; // Send byte
sts 156,R16
.dbline 793
; #endif
; break;
xjmp L144
L143:
.dbline 794
; default : return false; //
clr R16
xjmp L142
L144:
.dbline 797
; }
;
; return true;
ldi R16,1
.dbline -2
L142:
xcall pop_gset2
.dbline 0 ; func end
ret
.dbsym r UART_TimeOut 20 s
.dbsym r Uart 18 c
.dbsym r c 16 c
.dbend
.dbfunc e HardwareFlowControl _HardwareFlowControl fV
; i -> R20,R21
; Uart -> R20
.even
_HardwareFlowControl::
xcall push_gset1
mov R20,R16
sbiw R28,2
.dbline -1
.dbline 801
; }
;
; void HardwareFlowControl(char Uart)
; { // do some hardware flow control - ie, set their CTS line accordingly
.dbline 804
; int i;
;
; switch (Uart)
clr R21
cpi R20,0
cpc R20,R21
breq L170
X24:
cpi R20,1
ldi R30,0
cpc R21,R30
breq L173
xjmp L167
X25:
.dbline 805
; {
L170:
.dbline 806
; case UART0 : i = RingBufBytesFree(sizeof(UART0_RxBuffer), UART0_RxBufferRd, UART0_RxBufferWr); // work out how many bytes we have free in our buffer
lds R2,_UART0_RxBufferWr
clr R3
std y+1,R3
std y+0,R2
lds R18,_UART0_RxBufferRd
clr R19
ldi R16,32
ldi R17,0
xcall _RingBufBytesFree
movw R20,R16
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