📄 main.lis
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0432 18F0 brlo L115
0434 .dbline 384
0434 2224 clr R2
0436 20920000 sts _UART1_RxBufferWr,R2
043A L115:
043A .dbline 387
043A ;
043A ; #ifdef ModemHandShaking
043A ; HardwareFlowControl(UART1); // tell em to hold it - if need be
043A 01E0 ldi R16,1
043C 0E940000 xcall _HardwareFlowControl
0440 .dbline -2
0440 L114:
0440 0E940000 xcall pop_lset
0444 .dbline 0 ; func end
0444 1895 reti
0446 .dbend
0446 .dbfunc e main _main fV
0446 ; i -> R10,R11
0446 ; j -> R12,R13
.even
0446 _main::
0446 2297 sbiw R28,2
0448 .dbline -1
0448 .dbline 413
0448 ; #endif
0448 ; }
0448 ;
0448 ; // *********************************************************************************
0448 ; /*
0448 ; #ifdef CPU_ATmega128
0448 ; void StackOverflowTest(u32 dw)
0448 ; {
0448 ; USB_Get(); // get data from USB
0448 ; USB_Send(); // send any data that needs sending via the USB
0448 ; USB_ProcessGet(); // process the rx'ed packet from the USB
0448 ;
0448 ; _StackCheck(); // check for stack overflow
0448 ;
0448 ; if (!WatchdogCounter) WatchdogCounter++; //
0448 ;
0448 ; dw++;
0448 ; StackOverflowTest(dw);
0448 ; }
0448 ; #endif
0448 ; */
0448 ; // *********************************************************************************
0448 ; // Main program here
0448 ;
0448 ; void main(void)
0448 ; {
0448 .dbline 416
0448 ; int i, j;
0448 ;
0448 ; Disable_Ints();
0448 F894 cli
044A .dbline 425
044A ;
044A ; // ****************************
044A ; // find out what caused the last reset
044A ;
044A ; #ifdef CPU_eZ8
044A ; LastResetReason = WDTCTL;
044A ; #endif
044A ; #ifdef CPU_ATmega128
044A ; LastResetReason = MCUCSR;
044A 24B6 in R2,0x34
044C 20920000 sts _LastResetReason,R2
0450 .dbline 426
0450 ; MCUCSR &= 0xE0; // clear the bits
0450 84B7 in R24,0x34
0452 807E andi R24,224
0454 84BF out 0x34,R24
0456 .dbline 433
0456 ; #endif
0456 ;
0456 ; // **********************
0456 ; // Define external memory mapping
0456 ;
0456 ; #ifdef CPU_ATmega128
0456 ; asm( ".area memory(abs)\n"
.area memory(abs)
.org 0x1100
1100 _SRAM:: .blkb 1
.text
0456 .dbline 452
0456 ; ".org 0x1100\n"
0456 ; " _SRAM:: .blkb 1\n"
0456 ; ".text\n");
0456 ; #endif
0456 ;
0456 ; // ****************************
0456 ; // set the watchdog timeout ASAP - you'll find the timeout value in common.h
0456 ; // see page 158 of the Z8F6423 product spec's pdf
0456 ; // the file config\Z8F6423.ini for the option bit settings - changing these makes no difference :(
0456 ;
0456 ; #ifdef CPU_eZ8
0456 ; WDTCTL = 0x55; // unlock the watchdog - so we can set it's time out
0456 ; WDTCTL = 0xAA; // " " "
0456 ; WDTU = (u8)((WatchdogTimeout >> 16) & 0xff); // Set the timeout
0456 ; WDTH = (u8)((WatchdogTimeout >> 8) & 0xff); // " " "
0456 ; WDTL = (u8)(WatchdogTimeout & 0xff); // " " "
0456 ; #endif
0456 ;
0456 ; Reset_WD();
0456 A895 wdr
0458 .dbline 455
0458 ;
0458 ; #ifdef CPU_ATmega128
0458 ; WDTCR |= (1 << WDCE) | (1 << WDE); // Enable watchdog config change
0458 81B5 in R24,0x21
045A 8861 ori R24,24
045C 81BD out 0x21,R24
045E .dbline 456
045E ; WDTCR = (1 << WDE) | (1 << WDP2) | (1 << WDP1) | (1 << WDP0); // Enable watchdog to 2 second time out
045E 8FE0 ldi R24,15
0460 81BD out 0x21,R24
0462 .dbline 503
0462 ; #endif
0462 ;
0462 ; // ****************************
0462 ; // disable all interrupts as default - or should i trust that the reset condition is reliable ?
0462 ;
0462 ; #ifdef CPU_eZ8
0462 ; IRQ0ENH = 0; // disable each individual interrupt
0462 ; IRQ0ENL = 0; //
0462 ; //
0462 ; IRQ1ENH = 0; //
0462 ; IRQ1ENL = 0; //
0462 ; //
0462 ; IRQ2ENH = 0; //
0462 ; IRQ2ENL = 0; //
0462 ; #endif
0462 ;
0462 ; // ****************************
0462 ; // set all ports to input state as default
0462 ;
0462 ; #ifdef CPU_eZ8
0462 ; PADD = 0xff; // as inputs
0462 ; PAADDR = 0; // clear to protect sub registers
0462 ; //
0462 ; PBDD = 0xff; // as inputs
0462 ; PBADDR = 0; // clear to protect sub registers
0462 ; //
0462 ; PCDD = 0xff; // as inputs
0462 ; PCADDR = 0; // clear to protect sub registers
0462 ; //
0462 ; PDDD = 0xff; // as inputs
0462 ; PDADDR = 0; // clear to protect sub registers
0462 ; //
0462 ; PEDD = 0xff; // as inputs
0462 ; PEADDR = 0; // clear to protect sub registers
0462 ; //
0462 ; PFDD = 0xff; // as inputs
0462 ; PFADDR = 0; // clear to protect sub registers
0462 ; //
0462 ; PGDD = 0xff; // as inputs
0462 ; PGADDR = 0; // clear to protect sub registers
0462 ; //
0462 ; PHDD = 0xff; // as inputs
0462 ; PHADDR = 0; // clear to protect sub registers
0462 ; #endif
0462 ;
0462 ; #ifdef CPU_ATmega128
0462 ; PORTA = 0xff; // enable pull-ups
0462 8FEF ldi R24,255
0464 8BBB out 0x1b,R24
0466 .dbline 504
0466 ; DDRA = 0x00; // as inputs
0466 2224 clr R2
0468 2ABA out 0x1a,R2
046A .dbline 506
046A ;
046A ; PORTB = 0xff; // enable pull-ups
046A 88BB out 0x18,R24
046C .dbline 507
046C ; DDRB = 0x00; // as inputs
046C 27BA out 0x17,R2
046E .dbline 509
046E ;
046E ; PORTC = 0xff; // enable pull-ups
046E 85BB out 0x15,R24
0470 .dbline 510
0470 ; DDRC = 0x00; // as inputs
0470 24BA out 0x14,R2
0472 .dbline 512
0472 ;
0472 ; PORTD = 0xff; // enable pull-ups
0472 82BB out 0x12,R24
0474 .dbline 513
0474 ; DDRD = 0x00; // as inputs
0474 21BA out 0x11,R2
0476 .dbline 515
0476 ;
0476 ; PORTE = 0xff; // enable pull-ups
0476 83B9 out 0x3,R24
0478 .dbline 516
0478 ; DDRE = 0x00; // as inputs
0478 22B8 out 0x2,R2
047A .dbline 518
047A ;
047A ; PORTF = 0xfc; // enable pull-ups
047A 8CEF ldi R24,252
047C 80936200 sts 98,R24
0480 .dbline 519
0480 ; DDRF = 0x00; // as inputs
0480 20926100 sts 97,R2
0484 .dbline 521
0484 ;
0484 ; PORTG = 0xff; // enable pull-ups
0484 8FEF ldi R24,255
0486 80936500 sts 101,R24
048A .dbline 522
048A ; DDRG = 0x00; // as inputs
048A 20926400 sts 100,R2
048E .dbline 528
048E ; #endif
048E ;
048E ; // ****************************
048E ; // delay a bit - stops irratic boot-ups when programming etc
048E ;
048E ; for (i = 0; i < 25; i++)
048E AA24 clr R10
0490 BB24 clr R11
0492 L118:
0492 .dbline 529
0492 ; {
0492 .dbline 530
0492 ; for (j = 0; j < 32767; j++)
0492 CC24 clr R12
0494 DD24 clr R13
0496 L122:
0496 .dbline 531
0496 .dbline 532
0496 A895 wdr
0498 .dbline 533
0498 L123:
0498 .dbline 530
0498 C601 movw R24,R12
049A 0196 adiw R24,1
049C 6C01 movw R12,R24
049E .dbline 530
049E 8F3F cpi R24,255
04A0 EFE7 ldi R30,127
04A2 9E07 cpc R25,R30
04A4 C4F3 brlt L122
04A6 .dbline 534
04A6 L119:
04A6 .dbline 528
04A6 C501 movw R24,R10
04A8 0196 adiw R24,1
04AA 5C01 movw R10,R24
04AC .dbline 528
04AC 8931 cpi R24,25
04AE E0E0 ldi R30,0
04B0 9E07 cpc R25,R30
04B2 7CF3 brlt L118
04B4 .dbline 566
04B4 ; {
04B4 ; Reset_WD();
04B4 ; }
04B4 ; }
04B4 ;
04B4 ; // ****************************
04B4 ;
04B4 ; #ifdef CPU_eZ8
04B4 ; RLed_ddPort &= ~(1 << RLed_Pin); // set as output
04B4 ; RLed_hdePort &= ~(1 << RLed_Pin); // disable high drive
04B4 ; RLed_addrPort = 0; // clear to protect sub registers
04B4 ; RLed_Off; //
04B4 ;
04B4 ; YLed_ddPor⌨️ 快捷键说明
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