📄 uart.lst
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1 .file "uart.c"
2 .arch atmega64
3 __SREG__ = 0x3f
4 __SP_H__ = 0x3e
5 __SP_L__ = 0x3d
6 __tmp_reg__ = 0
7 __zero_reg__ = 1
8 .global __do_copy_data
9 .global __do_clear_bss
17 .Ltext0:
18 .global Tx1Tail
19 .global Tx1Tail
20 .section .bss
23 Tx1Tail:
24 0000 0000 .skip 2,0
25 .global Rx1Tail
26 .global Rx1Tail
29 Rx1Tail:
30 0002 0000 .skip 2,0
31 .global Tx1Head
32 .global Tx1Head
35 Tx1Head:
36 0004 0000 .skip 2,0
37 .global Rx1Head
38 .global Rx1Head
41 Rx1Head:
42 0006 0000 .skip 2,0
43 .text
44 .global InitUart
46 InitUart:
47 .LFB2:
48 .LM1:
49 /* prologue: frame size=0 */
50 /* prologue end (size=0) */
51 .LM2:
52 0000 1092 9B00 sts 155,__zero_reg__
53 .LM3:
54 0004 88ED ldi r24,lo8(-40)
55 0006 8093 9A00 sts 154,r24
56 .LM4:
57 000a 86E0 ldi r24,lo8(6)
58 000c 8093 9D00 sts 157,r24
59 .LM5:
60 0010 1092 9800 sts 152,__zero_reg__
61 .LM6:
62 0014 8CE0 ldi r24,lo8(12)
63 0016 8093 9900 sts 153,r24
64 /* epilogue: frame size=0 */
65 001a 0895 ret
66 /* epilogue end (size=1) */
67 /* function InitUart size 14 (13) */
68 .LFE2:
70 .global __vector_30
72 __vector_30:
73 .LFB3:
74 .LM7:
75 /* prologue: frame size=0 */
76 /* prologue: naked */
77 /* prologue end (size=0) */
78 .LM8:
79 001c 0E94 0000 call IntProlog
80 .LM9:
81 0020 2091 0000 lds r18,Rx1Tail
82 0024 3091 0000 lds r19,(Rx1Tail)+1
83 0028 F901 movw r30,r18
84 002a E050 subi r30,lo8(-(Rx1Buffer))
85 002c F040 sbci r31,hi8(-(Rx1Buffer))
86 002e 8091 9C00 lds r24,156
87 0032 8083 st Z,r24
88 .LM10:
89 0034 C901 movw r24,r18
90 0036 0196 adiw r24,1
91 0038 9093 0000 sts (Rx1Tail)+1,r25
92 003c 8093 0000 sts Rx1Tail,r24
93 0040 8436 cpi r24,100
94 0042 9105 cpc r25,__zero_reg__
95 0044 20F0 brlo .L3
96 .LM11:
97 0046 1092 0000 sts (Rx1Tail)+1,__zero_reg__
98 004a 1092 0000 sts Rx1Tail,__zero_reg__
99 .L3:
100 .LM12:
101 004e 0E94 0000 call Epilog
102 /* epilogue: frame size=0 */
103 /* epilogue: naked */
104 /* epilogue end (size=0) */
105 /* function __vector_30 size 27 (27) */
106 .LFE3:
108 .global __vector_32
110 __vector_32:
111 .LFB4:
112 .LM13:
113 /* prologue: frame size=0 */
114 /* prologue: naked */
115 /* prologue end (size=0) */
116 .LM14:
117 0052 0E94 0000 call IntProlog
118 .LM15:
119 0056 8091 0000 lds r24,Tx1Tail
120 005a 9091 0000 lds r25,(Tx1Tail)+1
121 005e 2091 0000 lds r18,Tx1Head
122 0062 3091 0000 lds r19,(Tx1Head)+1
123 0066 8217 cp r24,r18
124 0068 9307 cpc r25,r19
125 006a 99F0 breq .L5
126 .LM16:
127 006c F901 movw r30,r18
128 006e E050 subi r30,lo8(-(Tx1Buffer))
129 0070 F040 sbci r31,hi8(-(Tx1Buffer))
130 0072 8081 ld r24,Z
131 0074 8093 9C00 sts 156,r24
132 .LM17:
133 0078 C901 movw r24,r18
134 007a 0196 adiw r24,1
135 007c 9093 0000 sts (Tx1Head)+1,r25
136 0080 8093 0000 sts Tx1Head,r24
137 0084 8436 cpi r24,100
138 0086 9105 cpc r25,__zero_reg__
139 0088 20F0 brlo .L5
140 008a 1092 0000 sts (Tx1Head)+1,__zero_reg__
141 008e 1092 0000 sts Tx1Head,__zero_reg__
142 .L5:
143 .LM18:
144 0092 0E94 0000 call Epilog
145 /* epilogue: frame size=0 */
146 /* epilogue: naked */
147 /* epilogue end (size=0) */
148 /* function __vector_32 size 34 (34) */
149 .LFE4:
151 .global GetUart1Data
153 GetUart1Data:
154 .LFB5:
155 .LM19:
156 /* prologue: frame size=0 */
157 /* prologue end (size=0) */
158 0096 DC01 movw r26,r24
159 .LM20:
160 0098 8091 0000 lds r24,Rx1Tail
161 009c 9091 0000 lds r25,(Rx1Tail)+1
162 00a0 E091 0000 lds r30,Rx1Head
163 00a4 F091 0000 lds r31,(Rx1Head)+1
164 00a8 8E17 cp r24,r30
165 00aa 9F07 cpc r25,r31
166 00ac B9F0 breq .L8
167 .LM21:
168 00ae E050 subi r30,lo8(-(Rx1Buffer))
169 00b0 F040 sbci r31,hi8(-(Rx1Buffer))
170 00b2 8081 ld r24,Z
171 00b4 8C93 st X,r24
172 .LM22:
173 00b6 8091 0000 lds r24,Rx1Head
174 00ba 9091 0000 lds r25,(Rx1Head)+1
175 00be 0196 adiw r24,1
176 00c0 9093 0000 sts (Rx1Head)+1,r25
177 00c4 8093 0000 sts Rx1Head,r24
178 00c8 8436 cpi r24,100
179 00ca 9105 cpc r25,__zero_reg__
180 00cc 20F0 brlo .L9
181 00ce 1092 0000 sts (Rx1Head)+1,__zero_reg__
182 00d2 1092 0000 sts Rx1Head,__zero_reg__
183 .L9:
184 .LM23:
185 00d6 81E0 ldi r24,lo8(1)
186 00d8 90E0 ldi r25,hi8(1)
187 00da 0895 ret
188 .L8:
189 .LM24:
190 00dc 80E0 ldi r24,lo8(0)
191 00de 90E0 ldi r25,hi8(0)
192 .LM25:
193 00e0 0895 ret
194 /* epilogue: frame size=0 */
195 /* epilogue: noreturn */
196 /* epilogue end (size=0) */
197 /* function GetUart1Data size 38 (38) */
198 .LFE5:
200 .global PutUart1Data
202 PutUart1Data:
203 .LFB6:
204 .LM26:
205 /* prologue: frame size=0 */
206 /* prologue end (size=0) */
207 .LM27:
208 00e2 2091 0000 lds r18,Tx1Tail
209 00e6 3091 0000 lds r19,(Tx1Tail)+1
210 00ea F901 movw r30,r18
211 00ec E050 subi r30,lo8(-(Tx1Buffer))
212 00ee F040 sbci r31,hi8(-(Tx1Buffer))
213 00f0 8083 st Z,r24
214 .LM28:
215 00f2 C901 movw r24,r18
216 00f4 0196 adiw r24,1
217 00f6 9093 0000 sts (Tx1Tail)+1,r25
218 00fa 8093 0000 sts Tx1Tail,r24
219 00fe 8436 cpi r24,100
220 0100 9105 cpc r25,__zero_reg__
221 0102 20F0 brlo .L12
222 .LM29:
223 0104 1092 0000 sts (Tx1Tail)+1,__zero_reg__
224 0108 1092 0000 sts Tx1Tail,__zero_reg__
225 .L12:
226 .LM30:
227 010c 2091 0000 lds r18,Tx1Tail
228 0110 3091 0000 lds r19,(Tx1Tail)+1
229 0114 8091 0000 lds r24,Tx1Head
230 0118 9091 0000 lds r25,(Tx1Head)+1
231 011c 2817 cp r18,r24
232 011e 3907 cpc r19,r25
233 0120 19F0 breq .L13
234 .LM31:
235 0122 81E0 ldi r24,lo8(1)
236 0124 90E0 ldi r25,hi8(1)
237 0126 0895 ret
238 .L13:
239 .LM32:
240 0128 80E0 ldi r24,lo8(0)
241 012a 90E0 ldi r25,hi8(0)
242 .LM33:
243 012c 0895 ret
244 /* epilogue: frame size=0 */
245 /* epilogue: noreturn */
246 /* epilogue end (size=0) */
247 /* function PutUart1Data size 38 (38) */
248 .LFE6:
250 .global StartUart1Send
252 StartUart1Send:
253 .LFB7:
254 .LM34:
255 /* prologue: frame size=0 */
256 /* prologue end (size=0) */
257 .L16:
258 .LM35:
259 012e 8091 9B00 lds r24,155
260 0132 85FF sbrs r24,5
261 0134 FCCF rjmp .L16
262 .LM36:
263 0136 2091 0000 lds r18,Tx1Head
264 013a 3091 0000 lds r19,(Tx1Head)+1
265 013e F901 movw r30,r18
266 0140 E050 subi r30,lo8(-(Tx1Buffer))
267 0142 F040 sbci r31,hi8(-(Tx1Buffer))
268 0144 8081 ld r24,Z
269 0146 8093 9C00 sts 156,r24
270 .LM37:
271 014a C901 movw r24,r18
272 014c 0196 adiw r24,1
273 014e 9093 0000 sts (Tx1Head)+1,r25
274 0152 8093 0000 sts Tx1Head,r24
275 0156 8436 cpi r24,100
276 0158 9105 cpc r25,__zero_reg__
277 015a 20F0 brlo .L15
278 015c 1092 0000 sts (Tx1Head)+1,__zero_reg__
279 0160 1092 0000 sts Tx1Head,__zero_reg__
280 .L15:
281 0164 0895 ret
282 /* epilogue: frame size=0 */
283 /* epilogue: noreturn */
284 /* epilogue end (size=0) */
285 /* function StartUart1Send size 28 (28) */
286 .LFE7:
288 .global SendUart1String
290 SendUart1String:
291 .LFB8:
292 .LM38:
293 /* prologue: frame size=0 */
294 0166 0F93 push r16
295 0168 1F93 push r17
296 016a CF93 push r28
297 016c DF93 push r29
298 /* prologue end (size=4) */
299 016e 8C01 movw r16,r24
300 0170 EB01 movw r28,r22
301 .LM39:
302 0172 6115 cp r22,__zero_reg__
303 0174 7105 cpc r23,__zero_reg__
304 0176 21F4 brne .L21
305 .LM40:
306 0178 18C0 rjmp .L20
307 .L28:
308 .LM41:
309 017a 60E0 ldi r22,lo8(0)
310 017c 70E0 ldi r23,hi8(0)
311 017e 15C0 rjmp .L20
312 .L21:
313 0180 2197 sbiw r28,1
314 0182 8FEF ldi r24,hi8(-1)
315 0184 CF3F cpi r28,lo8(-1)
316 0186 D807 cpc r29,r24
317 0188 61F0 breq .L27
318 .L25:
319 .LM42:
320 018a F801 movw r30,r16
321 018c 8191 ld r24,Z+
322 018e 8F01 movw r16,r30
323 0190 0E94 0000 call PutUart1Data
324 0194 8823 tst r24
325 0196 89F3 breq .L28
326 .LM43:
327 0198 2197 sbiw r28,1
328 019a FFEF ldi r31,hi8(-1)
329 019c CF3F cpi r28,lo8(-1)
330 019e DF07 cpc r29,r31
331 01a0 A1F7 brne .L25
332 .L27:
333 .LM44:
334 01a2 0E94 0000 call StartUart1Send
335 .LM45:
336 01a6 61E0 ldi r22,lo8(1)
337 01a8 70E0 ldi r23,hi8(1)
338 .L20:
339 .LM46:
340 01aa CB01 movw r24,r22
341 /* epilogue: frame size=0 */
342 01ac DF91 pop r29
343 01ae CF91 pop r28
344 01b0 1F91 pop r17
345 01b2 0F91 pop r16
346 01b4 0895 ret
347 /* epilogue end (size=5) */
348 /* function SendUart1String size 40 (31) */
349 .LFE8:
351 .comm Rx1Buffer,100,1
352 .comm Tx1Buffer,100,1
353 .Letext0:
DEFINED SYMBOLS
*ABS*:00000000 uart.c
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:3 *ABS*:0000003f __SREG__
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:4 *ABS*:0000003e __SP_H__
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:5 *ABS*:0000003d __SP_L__
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:6 *ABS*:00000000 __tmp_reg__
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:7 *ABS*:00000001 __zero_reg__
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:23 .bss:00000000 Tx1Tail
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:29 .bss:00000002 Rx1Tail
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:35 .bss:00000004 Tx1Head
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:41 .bss:00000006 Rx1Head
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:46 .text:00000000 InitUart
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:72 .text:0000001c __vector_30
*COM*:00000064 Rx1Buffer
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:110 .text:00000052 __vector_32
*COM*:00000064 Tx1Buffer
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:153 .text:00000096 GetUart1Data
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:202 .text:000000e2 PutUart1Data
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:252 .text:0000012e StartUart1Send
C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/cc4Caaaa.s:290 .text:00000166 SendUart1String
UNDEFINED SYMBOLS
__do_copy_data
__do_clear_bss
IntProlog
Epilog
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