📄 lpc2400.s
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;// <o7.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.24..25> PCLK_MCI: Peripheral Clock Selection for MCI
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// </h>
;// </e>
CLOCK_SETUP EQU 1
SCS_Val EQU 0x00000020
CLKSRCSEL_Val EQU 0x00000001
PLLCFG_Val EQU 0x0000000B
CCLKCFG_Val EQU 0x00000004
USBCLKCFG_Val EQU 0x00000005
PCLKSEL0_Val EQU 0x00000000
PCLKSEL1_Val EQU 0x00000000
;----------------------- Memory Accelerator Module (MAM) Definitions -----------
MAM_BASE EQU 0xE01FC000 ; MAM Base Address
MAMCR_OFS EQU 0x00 ; MAM Control Offset
MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
;// <e> MAM Setup
;// <o1.0..1> MAM Control
;// <0=> Disabled
;// <1=> Partially Enabled
;// <2=> Fully Enabled
;// <i> Mode
;// <o2.0..2> MAM Timing
;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
;// <i> Fetch Cycles
;// </e>
MAM_SETUP EQU 1
MAMCR_Val EQU 0x00000002
MAMTIM_Val EQU 0x00000004
;----------------------- Pin Connect Block Definitions -------------------------
PCB_BASE EQU 0xE002C000 ; PCB Base Address
PINSEL0_OFS EQU 0x00 ; PINSEL0 Address Offset
PINSEL1_OFS EQU 0x04 ; PINSEL1 Address Offset
PINSEL2_OFS EQU 0x08 ; PINSEL2 Address Offset
PINSEL3_OFS EQU 0x0C ; PINSEL3 Address Offset
PINSEL4_OFS EQU 0x10 ; PINSEL4 Address Offset
PINSEL5_OFS EQU 0x14 ; PINSEL5 Address Offset
PINSEL6_OFS EQU 0x18 ; PINSEL6 Address Offset
PINSEL7_OFS EQU 0x1C ; PINSEL7 Address Offset
PINSEL8_OFS EQU 0x20 ; PINSEL8 Address Offset
PINSEL9_OFS EQU 0x24 ; PINSEL9 Address Offset
PINSEL10_OFS EQU 0x28 ; PINSEL10 Address Offset
;----------------------- External Memory Controller (EMC) Definitons -----------
EMC_BASE EQU 0xFFE08000 ; EMC Base Address
EMC_CTRL_OFS EQU 0x000
EMC_STAT_OFS EQU 0x004
EMC_CONFIG_OFS EQU 0x008
EMC_DYN_CTRL_OFS EQU 0x020
EMC_DYN_RFSH_OFS EQU 0x024
EMC_DYN_RD_CFG_OFS EQU 0x028
EMC_DYN_RP_OFS EQU 0x030
EMC_DYN_RAS_OFS EQU 0x034
EMC_DYN_SREX_OFS EQU 0x038
EMC_DYN_APR_OFS EQU 0x03C
EMC_DYN_DAL_OFS EQU 0x040
EMC_DYN_WR_OFS EQU 0x044
EMC_DYN_RC_OFS EQU 0x048
EMC_DYN_RFC_OFS EQU 0x04C
EMC_DYN_XSR_OFS EQU 0x050
EMC_DYN_RRD_OFS EQU 0x054
EMC_DYN_MRD_OFS EQU 0x058
EMC_DYN_CFG0_OFS EQU 0x100
EMC_DYN_RASCAS0_OFS EQU 0x104
EMC_DYN_CFG1_OFS EQU 0x140
EMC_DYN_RASCAS1_OFS EQU 0x144
EMC_DYN_CFG2_OFS EQU 0x160
EMC_DYN_RASCAS2_OFS EQU 0x164
EMC_DYN_CFG3_OFS EQU 0x180
EMC_DYN_RASCAS3_OFS EQU 0x184
EMC_STA_CFG0_OFS EQU 0x200
EMC_STA_WWEN0_OFS EQU 0x204
EMC_STA_WOEN0_OFS EQU 0x208
EMC_STA_WRD0_OFS EQU 0x20C
EMC_STA_WPAGE0_OFS EQU 0x210
EMC_STA_WWR0_OFS EQU 0x214
EMC_STA_WTURN0_OFS EQU 0x218
EMC_STA_CFG1_OFS EQU 0x220
EMC_STA_WWEN1_OFS EQU 0x224
EMC_STA_WOEN1_OFS EQU 0x228
EMC_STA_WRD1_OFS EQU 0x22C
EMC_STA_WPAGE1_OFS EQU 0x230
EMC_STA_WWR1_OFS EQU 0x234
EMC_STA_WTURN1_OFS EQU 0x238
EMC_STA_CFG2_OFS EQU 0x240
EMC_STA_WWEN2_OFS EQU 0x244
EMC_STA_WOEN2_OFS EQU 0x248
EMC_STA_WRD2_OFS EQU 0x24C
EMC_STA_WPAGE2_OFS EQU 0x250
EMC_STA_WWR2_OFS EQU 0x254
EMC_STA_WTURN2_OFS EQU 0x258
EMC_STA_CFG3_OFS EQU 0x260
EMC_STA_WWEN3_OFS EQU 0x264
EMC_STA_WOEN3_OFS EQU 0x268
EMC_STA_WRD3_OFS EQU 0x26C
EMC_STA_WPAGE3_OFS EQU 0x270
EMC_STA_WWR3_OFS EQU 0x274
EMC_STA_WTURN3_OFS EQU 0x278
EMC_STA_EXT_W_OFS EQU 0x880
; Constants
NORMAL_CMD EQU (0x0 << 7) ; NORMAL Command
MODE_CMD EQU (0x1 << 7) ; MODE Command
PALL_CMD EQU (0x2 << 7) ; Precharge All Command
NOP_CMD EQU (0x3 << 7) ; NOP Command
BUFEN_Const EQU (1 << 19) ; Buffer enable bit
EMC_PCONP_Const EQU (1 << 11) ; PCONP val to enable power for EMC
; External Memory Pins definitions
; pin functions for SDRAM, NOR and NAND flash interfacing
EMC_PINSEL5_Val EQU 0x05010115 ; !CAS, !RAS, CLKOUT0, !DYCS0, DQMOUT0, DQMOUT1
EMC_PINSEL6_Val EQU 0x55555555 ; D0 .. D15
EMC_PINSEL8_Val EQU 0x55555555 ; A0 .. A15
EMC_PINSEL9_Val EQU 0x50055555; ; A16 .. A23, !OE, !WE, !CS0, !CS1
;// External Memory Controller Setup (EMC) ---------------------------------
;// <e> External Memory Controller Setup (EMC)
EMC_SETUP EQU 0
;// <h> EMC Control Register (EMCControl)
;// <i> Controls operation of the memory controller
;// <o0.2> L: Low-power mode enable
;// <o0.1> M: Address mirror enable
;// <o0.0> E: EMC enable
;// </h>
EMC_CTRL_Val EQU 0x00000001
;// <h> EMC Configuration Register (EMCConfig)
;// <i> Configures operation of the memory controller
;// <o0.8> CCLK: CLKOUT ratio
;// <0=> 1:1
;// <1=> 1:2
;// <o0.0> Endian mode
;// <0=> Little-endian
;// <1=> Big-endian
;// </h>
EMC_CONFIG_Val EQU 0x00000000
;// Dynamic Memory Interface Setup ---------------------------------------
;// <e> Dynamic Memory Interface Setup
EMC_DYNAMIC_SETUP EQU 1
;// <h> Dynamic Memory Refresh Timer Register (EMCDynamicRefresh)
;// <i> Configures dynamic memory refresh operation
;// <o0.0..10> REFRESH: Refresh timer <0x000-0x7FF>
;// <i> 0 = refresh disabled, 0x01-0x7FF: value * 16 CCLKS
;// </h>
EMC_DYN_RFSH_Val EQU 0x0000001C
;// <h> Dynamic Memory Read Configuration Register (EMCDynamicReadConfig)
;// <i> Configures the dynamic memory read strategy
;// <o0.0..1> RD: Read data strategy
;// <0=> Clock out delayed strategy
;// <1=> Command delayed strategy
;// <2=> Command delayed strategy plus one clock cycle
;// <3=> Command delayed strategy plus two clock cycles
;// </h>
EMC_DYN_RD_CFG_Val EQU 0x00000001
;// <h> Dynamic Memory Timings
;// <h> Dynamic Memory Percentage Command Period Register (EMCDynamictRP)
;// <o0.0..3> tRP: Precharge command period <1-16> <#-1>
;// <i> The delay is in EMCCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tRP
;// </h>
;// <h> Dynamic Memory Active to Precharge Command Period Register (EMCDynamictRAS)
;// <o1.0..3> tRAS: Active to precharge command period <1-16> <#-1>
;// <i> The delay is in EMCCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tRAS
;// </h>
;// <h> Dynamic Memory Self-refresh Exit Time Register (EMCDynamictSREX)
;// <o2.0..3> tSREX: Self-refresh exit time <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tSREX,
;// <i> for devices without this parameter you use the same value as tXSR
;// </h>
;// <h> Dynamic Memory Last Data Out to Active Time Register (EMCDynamictAPR)
;// <o3.0..3> tAPR: Last-data-out to active command time <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tAPR
;// </h>
;// <h> Dynamic Memory Data-in to Active Command Time Register (EMCDynamictDAL)
;// <o4.0..3> tDAL: Data-in to active command time <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tDAL or tAPW
;// </h>
;// <h> Dynamic Memory Write Recovery Time Register (EMCDynamictWR)
;// <o5.0..3> tWR: Write recovery time <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL
;// </h>
;// <h> Dynamic Memory Active to Active Command Period Register (EMCDynamictRC)
;// <o6.0..4> tRC: Active to active command period <1-32> <#-1>
;// <i> The delay is in CCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tRC
;// </h>
;// <h> Dynamic Memory Auto-refresh Period Register (EMCDynamictRFC)
;// <o7.0..4> tRFC: Auto-refresh period and auto-refresh to active command period <1-32> <#-1>
;// <i> The delay is in CCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tRFC or tRC
;// </h>
;// <h> Dynamic Memory Exit Self-refresh Register (EMCDynamictXSR)
;// <o8.0..4> tXSR: Exit self-refresh to active command time <1-32> <#-1>
;// <i> The delay is in CCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tXSR
;// </h>
;// <h> Dynamic Memory Active Bank A to Active Bank B Time Register (EMCDynamicRRD)
;// <o9.0..3> tRRD: Active bank A to active bank B latency <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tRRD
;// </h>
;// <h> Dynamic Memory Load Mode Register to Active Command Time (EMCDynamictMRD)
;// <o10.0..3> tMRD: Load mode register to active command time <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// <i> This value is normally found in SDRAM data sheets as tMRD or tRSA
;// </h>
;// </h>
EMC_DYN_RP_Val EQU 0x00000002
EMC_DYN_RAS_Val EQU 0x00000003
EMC_DYN_SREX_Val EQU 0x00000007
EMC_DYN_APR_Val EQU 0x00000002
EMC_DYN_DAL_Val EQU 0x00000005
EMC_DYN_WR_Val EQU 0x00000001
EMC_DYN_RC_Val EQU 0x00000005
EMC_DYN_RFC_Val EQU 0x00000005
EMC_DYN_XSR_Val EQU 0x00000007
EMC_DYN_RRD_Val EQU 0x00000001
EMC_DYN_MRD_Val EQU 0x00000002
;// <e> Configure External Bus Behaviour for Dynamic CS0 Area
EMC_DYNCS0_SETUP EQU 1
;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig0)
;// <i> Defines the configuration information for the dynamic memory CS0
;// <o0.20> P: Write protect
;// <o0.19> B: Buffer enable
;// <o0.14> AM 14: External bus data width
;// <0=> 16 bit
;// <1=> 32 bit
;// <o0.12> AM 12: External bus memory type
;// <0=> High-performance
;// <1=> Low-power SDRAM
;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column)
;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9
;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8
;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9
;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8
;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10
;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9
;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10
;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9
;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11
;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10
;// <o0.3..4> MD: Memory device
;// <0=> SDRAM
;// <1=> Low-power SDRAM
;// <2=> Micron SyncFlash
;// </h>
EMC_DYN_CFG0_Val EQU 0x00080680
;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0)
;// <i> Controls the RAS and CAS latencies for the dynamic memory CS0
;// <o0.8..9> CAS: CAS latency
;// <1=> One CCLK cycle
;// <2=> Two CCLK cycles
;// <3=> Three CCLK cycles
;// <o0.0..1> RAS: RAS latency (active to read/write delay)
;// <1=> One CCLK cycle
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