barrel_shifter.tan.rpt

桶型移位寄存器 用于多种场合 可放心下载

+-------------------------------------------------------------------------------+
; tco                                                                           ;
+-------+--------------+------------+-----------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To         ; From Clock ;
+-------+--------------+------------+-----------------+------------+------------+
; N/A   ; None         ; 7.622 ns   ; dataout[5]~reg0 ; dataout[5] ; clk        ;
; N/A   ; None         ; 6.340 ns   ; dataout[6]~reg0 ; dataout[6] ; clk        ;
; N/A   ; None         ; 6.324 ns   ; dataout[2]~reg0 ; dataout[2] ; clk        ;
; N/A   ; None         ; 6.317 ns   ; dataout[0]~reg0 ; dataout[0] ; clk        ;
; N/A   ; None         ; 6.292 ns   ; dataout[1]~reg0 ; dataout[1] ; clk        ;
; N/A   ; None         ; 6.000 ns   ; dataout[3]~reg0 ; dataout[3] ; clk        ;
; N/A   ; None         ; 5.992 ns   ; dataout[4]~reg0 ; dataout[4] ; clk        ;
; N/A   ; None         ; 5.990 ns   ; dataout[7]~reg0 ; dataout[7] ; clk        ;
+-------+--------------+------------+-----------------+------------+------------+


+----------------------------------------------------------------------------------+
; th                                                                               ;
+---------------+-------------+-----------+-----------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To              ; To Clock ;
+---------------+-------------+-----------+-----------+-----------------+----------+
; N/A           ; None        ; 0.749 ns  ; datain[5] ; dataout[5]~reg0 ; clk      ;
; N/A           ; None        ; 0.746 ns  ; datain[4] ; dataout[4]~reg0 ; clk      ;
; N/A           ; None        ; -3.358 ns ; datain[3] ; dataout[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.531 ns ; datain[0] ; dataout[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.729 ns ; datain[2] ; dataout[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.788 ns ; datain[1] ; dataout[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.818 ns ; ld        ; dataout[6]~reg0 ; clk      ;
; N/A           ; None        ; -3.819 ns ; ld        ; dataout[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.845 ns ; datain[7] ; dataout[7]~reg0 ; clk      ;
; N/A           ; None        ; -3.878 ns ; datain[6] ; dataout[6]~reg0 ; clk      ;
; N/A           ; None        ; -4.034 ns ; ld        ; dataout[1]~reg0 ; clk      ;
; N/A           ; None        ; -4.036 ns ; ld        ; dataout[2]~reg0 ; clk      ;
; N/A           ; None        ; -4.038 ns ; ld        ; dataout[4]~reg0 ; clk      ;
; N/A           ; None        ; -4.042 ns ; ld        ; dataout[5]~reg0 ; clk      ;
; N/A           ; None        ; -4.042 ns ; ld        ; dataout[3]~reg0 ; clk      ;
; N/A           ; None        ; -4.043 ns ; ld        ; dataout[7]~reg0 ; clk      ;
+---------------+-------------+-----------+-----------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Fri Oct 26 16:11:19 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off barrel_shifter -c barrel_shifter --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "dataout[5]~reg0" and destination register "dataout[6]~reg0"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.549 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout[5]~reg0'
            Info: 2: + IC(0.315 ns) + CELL(0.150 ns) = 0.465 ns; Loc. = LCCOMB_X1_Y6_N10; Fanout = 1; COMB Node = 'dataout~102'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.549 ns; Loc. = LCFF_X1_Y6_N11; Fanout = 2; REG Node = 'dataout[6]~reg0'
            Info: Total cell delay = 0.234 ns ( 42.62 % )
            Info: Total interconnect delay = 0.315 ns ( 57.38 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.323 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N11; Fanout = 2; REG Node = 'dataout[6]~reg0'
                Info: Total cell delay = 1.516 ns ( 65.26 % )
                Info: Total interconnect delay = 0.807 ns ( 34.74 % )
            Info: - Longest clock path from clock "clk" to source register is 2.323 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout[5]~reg0'
                Info: Total cell delay = 1.516 ns ( 65.26 % )
                Info: Total interconnect delay = 0.807 ns ( 34.74 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "dataout[7]~reg0" (data pin = "ld", clock pin = "clk") is 4.273 ns
    Info: + Longest pin to register delay is 6.632 ns
        Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_K15; Fanout = 8; PIN Node = 'ld'
        Info: 2: + IC(5.278 ns) + CELL(0.438 ns) = 6.548 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; COMB Node = 'dataout~103'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.632 ns; Loc. = LCFF_X1_Y6_N23; Fanout = 2; REG Node = 'dataout[7]~reg0'
        Info: Total cell delay = 1.354 ns ( 20.42 % )
        Info: Total interconnect delay = 5.278 ns ( 79.58 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.323 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N23; Fanout = 2; REG Node = 'dataout[7]~reg0'
        Info: Total cell delay = 1.516 ns ( 65.26 % )
        Info: Total interconnect delay = 0.807 ns ( 34.74 % )
Info: tco from clock "clk" to destination pin "dataout[5]" through register "dataout[5]~reg0" is 7.622 ns
    Info: + Longest clock path from clock "clk" to source register is 2.323 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout[5]~reg0'
        Info: Total cell delay = 1.516 ns ( 65.26 % )
        Info: Total interconnect delay = 0.807 ns ( 34.74 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.049 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout[5]~reg0'
        Info: 2: + IC(2.437 ns) + CELL(2.612 ns) = 5.049 ns; Loc. = PIN_G15; Fanout = 0; PIN Node = 'dataout[5]'
        Info: Total cell delay = 2.612 ns ( 51.73 % )
        Info: Total interconnect delay = 2.437 ns ( 48.27 % )
Info: th for register "dataout[5]~reg0" (data pin = "datain[5]", clock pin = "clk") is 0.749 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.323 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout[5]~reg0'
        Info: Total cell delay = 1.516 ns ( 65.26 % )
        Info: Total interconnect delay = 0.807 ns ( 34.74 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 1.840 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_J1; Fanout = 1; PIN Node = 'datain[5]'
        Info: 2: + IC(0.357 ns) + CELL(0.420 ns) = 1.756 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 1; COMB Node = 'dataout~101'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.840 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout[5]~reg0'
        Info: Total cell delay = 1.483 ns ( 80.60 % )
        Info: Total interconnect delay = 0.357 ns ( 19.40 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Fri Oct 26 16:11:21 2007
    Info: Elapsed time: 00:00:02