📄 barrel_shifter.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register dataout\[5\]~reg0 dataout\[6\]~reg0 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"dataout\[5\]~reg0\" and destination register \"dataout\[6\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.549 ns + Longest register register " "Info: + Longest register to register delay is 0.549 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dataout\[5\]~reg0 1 REG LCFF_X1_Y6_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[5]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.315 ns) + CELL(0.150 ns) 0.465 ns dataout~102 2 COMB LCCOMB_X1_Y6_N10 1 " "Info: 2: + IC(0.315 ns) + CELL(0.150 ns) = 0.465 ns; Loc. = LCCOMB_X1_Y6_N10; Fanout = 1; COMB Node = 'dataout~102'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.465 ns" { dataout[5]~reg0 dataout~102 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.549 ns dataout\[6\]~reg0 3 REG LCFF_X1_Y6_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.549 ns; Loc. = LCFF_X1_Y6_N11; Fanout = 2; REG Node = 'dataout\[6\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { dataout~102 dataout[6]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 42.62 % ) " "Info: Total cell delay = 0.234 ns ( 42.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.315 ns ( 57.38 % ) " "Info: Total interconnect delay = 0.315 ns ( 57.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.549 ns" { dataout[5]~reg0 dataout~102 dataout[6]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.549 ns" { dataout[5]~reg0 dataout~102 dataout[6]~reg0 } { 0.000ns 0.315ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.323 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.685 ns) + CELL(0.537 ns) 2.323 ns dataout\[6\]~reg0 3 REG LCFF_X1_Y6_N11 2 " "Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N11; Fanout = 2; REG Node = 'dataout\[6\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { clk~clkctrl dataout[6]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 65.26 % ) " "Info: Total cell delay = 1.516 ns ( 65.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.807 ns ( 34.74 % ) " "Info: Total interconnect delay = 0.807 ns ( 34.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[6]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[6]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.323 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.685 ns) + CELL(0.537 ns) 2.323 ns dataout\[5\]~reg0 3 REG LCFF_X1_Y6_N19 2 " "Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 65.26 % ) " "Info: Total cell delay = 1.516 ns ( 65.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.807 ns ( 34.74 % ) " "Info: Total interconnect delay = 0.807 ns ( 34.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[5]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[6]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[6]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[5]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.549 ns" { dataout[5]~reg0 dataout~102 dataout[6]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.549 ns" { dataout[5]~reg0 dataout~102 dataout[6]~reg0 } { 0.000ns 0.315ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[6]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[6]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[5]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[6]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { dataout[6]~reg0 } { } { } "" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dataout\[7\]~reg0 ld clk 4.273 ns register " "Info: tsu for register \"dataout\[7\]~reg0\" (data pin = \"ld\", clock pin = \"clk\") is 4.273 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.632 ns + Longest pin register " "Info: + Longest pin to register delay is 6.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns ld 1 PIN PIN_K15 8 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_K15; Fanout = 8; PIN Node = 'ld'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { ld } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.278 ns) + CELL(0.438 ns) 6.548 ns dataout~103 2 COMB LCCOMB_X1_Y6_N22 1 " "Info: 2: + IC(5.278 ns) + CELL(0.438 ns) = 6.548 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; COMB Node = 'dataout~103'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.716 ns" { ld dataout~103 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.632 ns dataout\[7\]~reg0 3 REG LCFF_X1_Y6_N23 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.632 ns; Loc. = LCFF_X1_Y6_N23; Fanout = 2; REG Node = 'dataout\[7\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { dataout~103 dataout[7]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.354 ns ( 20.42 % ) " "Info: Total cell delay = 1.354 ns ( 20.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.278 ns ( 79.58 % ) " "Info: Total interconnect delay = 5.278 ns ( 79.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { ld dataout~103 dataout[7]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { ld ld~combout dataout~103 dataout[7]~reg0 } { 0.000ns 0.000ns 5.278ns 0.000ns } { 0.000ns 0.832ns 0.438ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.323 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.685 ns) + CELL(0.537 ns) 2.323 ns dataout\[7\]~reg0 3 REG LCFF_X1_Y6_N23 2 " "Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N23; Fanout = 2; REG Node = 'dataout\[7\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { clk~clkctrl dataout[7]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 65.26 % ) " "Info: Total cell delay = 1.516 ns ( 65.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.807 ns ( 34.74 % ) " "Info: Total interconnect delay = 0.807 ns ( 34.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[7]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[7]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { ld dataout~103 dataout[7]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { ld ld~combout dataout~103 dataout[7]~reg0 } { 0.000ns 0.000ns 5.278ns 0.000ns } { 0.000ns 0.832ns 0.438ns 0.084ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[7]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[7]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[5\] dataout\[5\]~reg0 7.622 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[5\]\" through register \"dataout\[5\]~reg0\" is 7.622 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.323 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.685 ns) + CELL(0.537 ns) 2.323 ns dataout\[5\]~reg0 3 REG LCFF_X1_Y6_N19 2 " "Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 65.26 % ) " "Info: Total cell delay = 1.516 ns ( 65.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.807 ns ( 34.74 % ) " "Info: Total interconnect delay = 0.807 ns ( 34.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[5]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.049 ns + Longest register pin " "Info: + Longest register to pin delay is 5.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dataout\[5\]~reg0 1 REG LCFF_X1_Y6_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[5]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.437 ns) + CELL(2.612 ns) 5.049 ns dataout\[5\] 2 PIN PIN_G15 0 " "Info: 2: + IC(2.437 ns) + CELL(2.612 ns) = 5.049 ns; Loc. = PIN_G15; Fanout = 0; PIN Node = 'dataout\[5\]'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.049 ns" { dataout[5]~reg0 dataout[5] } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.612 ns ( 51.73 % ) " "Info: Total cell delay = 2.612 ns ( 51.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.437 ns ( 48.27 % ) " "Info: Total interconnect delay = 2.437 ns ( 48.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.049 ns" { dataout[5]~reg0 dataout[5] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.049 ns" { dataout[5]~reg0 dataout[5] } { 0.000ns 2.437ns } { 0.000ns 2.612ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[5]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.049 ns" { dataout[5]~reg0 dataout[5] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.049 ns" { dataout[5]~reg0 dataout[5] } { 0.000ns 2.437ns } { 0.000ns 2.612ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dataout\[5\]~reg0 datain\[5\] clk 0.749 ns register " "Info: th for register \"dataout\[5\]~reg0\" (data pin = \"datain\[5\]\", clock pin = \"clk\") is 0.749 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.323 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.685 ns) + CELL(0.537 ns) 2.323 ns dataout\[5\]~reg0 3 REG LCFF_X1_Y6_N19 2 " "Info: 3: + IC(0.685 ns) + CELL(0.537 ns) = 2.323 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 65.26 % ) " "Info: Total cell delay = 1.516 ns ( 65.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.807 ns ( 34.74 % ) " "Info: Total interconnect delay = 0.807 ns ( 34.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[5]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" { } { { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.840 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns datain\[5\] 1 PIN PIN_J1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_J1; Fanout = 1; PIN Node = 'datain\[5\]'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { datain[5] } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.420 ns) 1.756 ns dataout~101 2 COMB LCCOMB_X1_Y6_N18 1 " "Info: 2: + IC(0.357 ns) + CELL(0.420 ns) = 1.756 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 1; COMB Node = 'dataout~101'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.777 ns" { datain[5] dataout~101 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.840 ns dataout\[5\]~reg0 3 REG LCFF_X1_Y6_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.840 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" { } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { dataout~101 dataout[5]~reg0 } "NODE_NAME" } } { "barrel_shifter.v" "" { Text "D:/d/barrel_shifter.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.483 ns ( 80.60 % ) " "Info: Total cell delay = 1.483 ns ( 80.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.357 ns ( 19.40 % ) " "Info: Total interconnect delay = 0.357 ns ( 19.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.840 ns" { datain[5] dataout~101 dataout[5]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "1.840 ns" { datain[5] datain[5]~combout dataout~101 dataout[5]~reg0 } { 0.000ns 0.000ns 0.357ns 0.000ns } { 0.000ns 0.979ns 0.420ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { clk clk~clkctrl dataout[5]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { clk clk~combout clk~clkctrl dataout[5]~reg0 } { 0.000ns 0.000ns 0.122ns 0.685ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.840 ns" { datain[5] dataout~101 dataout[5]~reg0 } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "1.840 ns" { datain[5] datain[5]~combout dataout~101 dataout[5]~reg0 } { 0.000ns 0.000ns 0.357ns 0.000ns } { 0.000ns 0.979ns 0.420ns 0.084ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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